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/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 2 -*-
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* vim: set ts=8 sts=2 et sw=2 tw=80:
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef jit_arm_MacroAssembler_arm_h
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#define jit_arm_MacroAssembler_arm_h
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#include "mozilla/DebugOnly.h"
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#include "jit/arm/Assembler-arm.h"
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#include "jit/JitFrames.h"
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#include "jit/MoveResolver.h"
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#include "vm/BigIntType.h"
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#include "vm/BytecodeUtil.h"
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namespace js {
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namespace jit {
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static Register CallReg = ip;
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static const int defaultShift = 3;
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JS_STATIC_ASSERT(1 << defaultShift == sizeof(JS::Value));
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// See documentation for ScratchTagScope and ScratchTagScopeRelease in
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// MacroAssembler-x64.h.
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class ScratchTagScope {
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const ValueOperand& v_;
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public:
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ScratchTagScope(MacroAssembler&, const ValueOperand& v) : v_(v) {}
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operator Register() { return v_.typeReg(); }
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void release() {}
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void reacquire() {}
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};
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class ScratchTagScopeRelease {
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public:
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explicit ScratchTagScopeRelease(ScratchTagScope*) {}
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};
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// MacroAssemblerARM is inheriting form Assembler defined in
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// Assembler-arm.{h,cpp}
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class MacroAssemblerARM : public Assembler {
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private:
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// Perform a downcast. Should be removed by Bug 996602.
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MacroAssembler& asMasm();
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const MacroAssembler& asMasm() const;
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protected:
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// On ARM, some instructions require a second scratch register. This
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// register defaults to lr, since it's non-allocatable (as it can be
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// clobbered by some instructions). Allow the baseline compiler to override
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// this though, since baseline IC stubs rely on lr holding the return
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// address.
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Register secondScratchReg_;
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public:
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Register getSecondScratchReg() const { return secondScratchReg_; }
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public:
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// Higher level tag testing code.
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// TODO: Can probably remove the Operand versions.
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Operand ToPayload(Operand base) const {
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return Operand(Register::FromCode(base.base()), base.disp());
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}
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Address ToPayload(const Address& base) const { return base; }
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protected:
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Operand ToType(Operand base) const {
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return Operand(Register::FromCode(base.base()),
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base.disp() + sizeof(void*));
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}
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Address ToType(const Address& base) const {
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return ToType(Operand(base)).toAddress();
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}
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Address ToPayloadAfterStackPush(const Address& base) const {
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// If we are based on StackPointer, pass over the type tag just pushed.
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if (base.base == StackPointer) {
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return Address(base.base, base.offset + sizeof(void*));
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}
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return ToPayload(base);
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}
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public:
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MacroAssemblerARM() : secondScratchReg_(lr) {}
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void setSecondScratchReg(Register reg) {
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MOZ_ASSERT(reg != ScratchRegister);
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secondScratchReg_ = reg;
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}
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void convertBoolToInt32(Register source, Register dest);
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void convertInt32ToDouble(Register src, FloatRegister dest);
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void convertInt32ToDouble(const Address& src, FloatRegister dest);
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void convertInt32ToDouble(const BaseIndex& src, FloatRegister dest);
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void convertUInt32ToFloat32(Register src, FloatRegister dest);
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void convertUInt32ToDouble(Register src, FloatRegister dest);
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void convertDoubleToFloat32(FloatRegister src, FloatRegister dest,
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Condition c = Always);
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void convertDoubleToInt32(FloatRegister src, Register dest, Label* fail,
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bool negativeZeroCheck = true);
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void convertFloat32ToInt32(FloatRegister src, Register dest, Label* fail,
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bool negativeZeroCheck = true);
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void convertFloat32ToDouble(FloatRegister src, FloatRegister dest);
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void convertInt32ToFloat32(Register src, FloatRegister dest);
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void convertInt32ToFloat32(const Address& src, FloatRegister dest);
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void wasmTruncateToInt32(FloatRegister input, Register output,
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MIRType fromType, bool isUnsigned, bool isSaturating,
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Label* oolEntry);
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void outOfLineWasmTruncateToIntCheck(FloatRegister input, MIRType fromType,
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MIRType toType, TruncFlags flags,
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Label* rejoin,
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wasm::BytecodeOffset trapOffset);
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// Somewhat direct wrappers for the low-level assembler funcitons
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// bitops. Attempt to encode a virtual alu instruction using two real
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// instructions.
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private:
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bool alu_dbl(Register src1, Imm32 imm, Register dest, ALUOp op, SBit s,
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Condition c);
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public:
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void ma_alu(Register src1, Imm32 imm, Register dest,
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AutoRegisterScope& scratch, ALUOp op, SBit s = LeaveCC,
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Condition c = Always);
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void ma_alu(Register src1, Operand2 op2, Register dest, ALUOp op,
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SBit s = LeaveCC, Condition c = Always);
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void ma_alu(Register src1, Operand op2, Register dest, ALUOp op,
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SBit s = LeaveCC, Condition c = Always);
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void ma_nop();
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BufferOffset ma_movPatchable(Imm32 imm, Register dest,
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Assembler::Condition c);
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BufferOffset ma_movPatchable(ImmPtr imm, Register dest,
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Assembler::Condition c);
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// To be used with Iter := InstructionIterator or BufferInstructionIterator.
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template <class Iter>
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static void ma_mov_patch(Imm32 imm, Register dest, Assembler::Condition c,
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RelocStyle rs, Iter iter);
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// ALU based ops
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// mov
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void ma_mov(Register src, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_mov(Imm32 imm, Register dest, Condition c = Always);
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void ma_mov(ImmWord imm, Register dest, Condition c = Always);
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void ma_mov(ImmGCPtr ptr, Register dest);
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// Shifts (just a move with a shifting op2)
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void ma_lsl(Imm32 shift, Register src, Register dst);
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void ma_lsr(Imm32 shift, Register src, Register dst);
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void ma_asr(Imm32 shift, Register src, Register dst);
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void ma_ror(Imm32 shift, Register src, Register dst);
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void ma_rol(Imm32 shift, Register src, Register dst);
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void ma_lsl(Register shift, Register src, Register dst);
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void ma_lsr(Register shift, Register src, Register dst);
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void ma_asr(Register shift, Register src, Register dst);
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void ma_ror(Register shift, Register src, Register dst);
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void ma_rol(Register shift, Register src, Register dst,
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AutoRegisterScope& scratch);
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// Move not (dest <- ~src)
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void ma_mvn(Register src1, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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// Negate (dest <- -src) implemented as rsb dest, src, 0
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void ma_neg(Register src, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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// And
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void ma_and(Register src, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_and(Register src1, Register src2, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_and(Imm32 imm, Register dest, AutoRegisterScope& scratch,
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SBit s = LeaveCC, Condition c = Always);
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void ma_and(Imm32 imm, Register src1, Register dest,
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AutoRegisterScope& scratch, SBit s = LeaveCC,
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Condition c = Always);
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// Bit clear (dest <- dest & ~imm) or (dest <- src1 & ~src2)
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void ma_bic(Imm32 imm, Register dest, AutoRegisterScope& scratch,
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SBit s = LeaveCC, Condition c = Always);
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// Exclusive or
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void ma_eor(Register src, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_eor(Register src1, Register src2, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_eor(Imm32 imm, Register dest, AutoRegisterScope& scratch,
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SBit s = LeaveCC, Condition c = Always);
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void ma_eor(Imm32 imm, Register src1, Register dest,
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AutoRegisterScope& scratch, SBit s = LeaveCC,
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Condition c = Always);
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// Or
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void ma_orr(Register src, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_orr(Register src1, Register src2, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_orr(Imm32 imm, Register dest, AutoRegisterScope& scratch,
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SBit s = LeaveCC, Condition c = Always);
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void ma_orr(Imm32 imm, Register src1, Register dest,
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AutoRegisterScope& scratch, SBit s = LeaveCC,
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Condition c = Always);
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// Arithmetic based ops.
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// Add with carry:
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void ma_adc(Imm32 imm, Register dest, AutoRegisterScope& scratch,
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SBit s = LeaveCC, Condition c = Always);
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void ma_adc(Register src, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_adc(Register src1, Register src2, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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// Add:
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void ma_add(Imm32 imm, Register dest, AutoRegisterScope& scratch,
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SBit s = LeaveCC, Condition c = Always);
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void ma_add(Register src1, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_add(Register src1, Register src2, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_add(Register src1, Operand op, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_add(Register src1, Imm32 op, Register dest,
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AutoRegisterScope& scratch, SBit s = LeaveCC,
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Condition c = Always);
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// Subtract with carry:
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void ma_sbc(Imm32 imm, Register dest, AutoRegisterScope& scratch,
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SBit s = LeaveCC, Condition c = Always);
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void ma_sbc(Register src1, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_sbc(Register src1, Register src2, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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// Subtract:
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void ma_sub(Imm32 imm, Register dest, AutoRegisterScope& scratch,
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SBit s = LeaveCC, Condition c = Always);
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void ma_sub(Register src1, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_sub(Register src1, Register src2, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_sub(Register src1, Operand op, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_sub(Register src1, Imm32 op, Register dest,
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AutoRegisterScope& scratch, SBit s = LeaveCC,
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Condition c = Always);
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// Reverse subtract:
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void ma_rsb(Imm32 imm, Register dest, AutoRegisterScope& scratch,
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SBit s = LeaveCC, Condition c = Always);
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void ma_rsb(Register src1, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_rsb(Register src1, Register src2, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_rsb(Register src1, Imm32 op2, Register dest,
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AutoRegisterScope& scratch, SBit s = LeaveCC,
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Condition c = Always);
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// Reverse subtract with carry:
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void ma_rsc(Imm32 imm, Register dest, AutoRegisterScope& scratch,
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SBit s = LeaveCC, Condition c = Always);
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void ma_rsc(Register src1, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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void ma_rsc(Register src1, Register src2, Register dest, SBit s = LeaveCC,
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Condition c = Always);
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// Compares/tests.
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// Compare negative (sets condition codes as src1 + src2 would):
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void ma_cmn(Register src1, Imm32 imm, AutoRegisterScope& scratch,
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Condition c = Always);
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void ma_cmn(Register src1, Register src2, Condition c = Always);
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void ma_cmn(Register src1, Operand op, Condition c = Always);
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// Compare (src - src2):
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void ma_cmp(Register src1, Imm32 imm, AutoRegisterScope& scratch,
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Condition c = Always);
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void ma_cmp(Register src1, ImmTag tag, Condition c = Always);
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void ma_cmp(Register src1, ImmWord ptr, AutoRegisterScope& scratch,
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Condition c = Always);
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void ma_cmp(Register src1, ImmGCPtr ptr, AutoRegisterScope& scratch,
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Condition c = Always);
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void ma_cmp(Register src1, Operand op, AutoRegisterScope& scratch,
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AutoRegisterScope& scratch2, Condition c = Always);
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void ma_cmp(Register src1, Register src2, Condition c = Always);
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// Test for equality, (src1 ^ src2):
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void ma_teq(Register src1, Imm32 imm, AutoRegisterScope& scratch,
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Condition c = Always);
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void ma_teq(Register src1, Register src2, Condition c = Always);
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void ma_teq(Register src1, Operand op, Condition c = Always);
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// Test (src1 & src2):
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void ma_tst(Register src1, Imm32 imm, AutoRegisterScope& scratch,
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Condition c = Always);
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void ma_tst(Register src1, Register src2, Condition c = Always);
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void ma_tst(Register src1, Operand op, Condition c = Always);
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// Multiplies. For now, there are only two that we care about.
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void ma_mul(Register src1, Register src2, Register dest);
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void ma_mul(Register src1, Imm32 imm, Register dest,
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AutoRegisterScope& scratch);
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Condition ma_check_mul(Register src1, Register src2, Register dest,
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AutoRegisterScope& scratch, Condition cond);
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Condition ma_check_mul(Register src1, Imm32 imm, Register dest,
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AutoRegisterScope& scratch, Condition cond);
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void ma_umull(Register src1, Imm32 imm, Register destHigh, Register destLow,
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AutoRegisterScope& scratch);
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void ma_umull(Register src1, Register src2, Register destHigh,
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Register destLow);
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// Fast mod, uses scratch registers, and thus needs to be in the assembler
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// implicitly assumes that we can overwrite dest at the beginning of the
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// sequence.
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void ma_mod_mask(Register src, Register dest, Register hold, Register tmp,
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AutoRegisterScope& scratch, AutoRegisterScope& scratch2,
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int32_t shift);
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// Mod - depends on integer divide instructions being supported.
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void ma_smod(Register num, Register div, Register dest,
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AutoRegisterScope& scratch);
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void ma_umod(Register num, Register div, Register dest,
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AutoRegisterScope& scratch);
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// Division - depends on integer divide instructions being supported.
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void ma_sdiv(Register num, Register div, Register dest,
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Condition cond = Always);
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void ma_udiv(Register num, Register div, Register dest,
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Condition cond = Always);
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// Misc operations
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void ma_clz(Register src, Register dest, Condition cond = Always);
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void ma_ctz(Register src, Register dest, AutoRegisterScope& scratch);
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// Memory:
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// Shortcut for when we know we're transferring 32 bits of data.
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void ma_dtr(LoadStore ls, Register rn, Imm32 offset, Register rt,
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AutoRegisterScope& scratch, Index mode = Offset,
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Condition cc = Always);
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void ma_dtr(LoadStore ls, Register rt, const Address& addr,
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AutoRegisterScope& scratch, Index mode, Condition cc);
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void ma_str(Register rt, DTRAddr addr, Index mode = Offset,
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Condition cc = Always);
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void ma_str(Register rt, const Address& addr, AutoRegisterScope& scratch,
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Index mode = Offset, Condition cc = Always);
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void ma_ldr(DTRAddr addr, Register rt, Index mode = Offset,
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Condition cc = Always);
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void ma_ldr(const Address& addr, Register rt, AutoRegisterScope& scratch,
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Index mode = Offset, Condition cc = Always);
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void ma_ldrb(DTRAddr addr, Register rt, Index mode = Offset,
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Condition cc = Always);
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void ma_ldrh(EDtrAddr addr, Register rt, Index mode = Offset,
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Condition cc = Always);
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void ma_ldrsh(EDtrAddr addr, Register rt, Index mode = Offset,
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Condition cc = Always);
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void ma_ldrsb(EDtrAddr addr, Register rt, Index mode = Offset,
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Condition cc = Always);
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void ma_ldrd(EDtrAddr addr, Register rt, mozilla::DebugOnly<Register> rt2,
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Index mode = Offset, Condition cc = Always);
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void ma_strb(Register rt, DTRAddr addr, Index mode = Offset,
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Condition cc = Always);
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void ma_strh(Register rt, EDtrAddr addr, Index mode = Offset,
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Condition cc = Always);
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void ma_strd(Register rt, mozilla::DebugOnly<Register> rt2, EDtrAddr addr,
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Index mode = Offset, Condition cc = Always);
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// Specialty for moving N bits of data, where n == 8,16,32,64.
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BufferOffset ma_dataTransferN(LoadStore ls, int size, bool IsSigned,
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Register rn, Register rm, Register rt,
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AutoRegisterScope& scratch, Index mode = Offset,
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Condition cc = Always, Scale scale = TimesOne);
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BufferOffset ma_dataTransferN(LoadStore ls, int size, bool IsSigned,
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Register rn, Register rm, Register rt,
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Index mode = Offset, Condition cc = Always);
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BufferOffset ma_dataTransferN(LoadStore ls, int size, bool IsSigned,
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Register rn, Imm32 offset, Register rt,
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AutoRegisterScope& scratch, Index mode = Offset,
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Condition cc = Always);
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void ma_pop(Register r);
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void ma_popn_pc(Imm32 n, AutoRegisterScope& scratch,
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AutoRegisterScope& scratch2);
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void ma_push(Register r);
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void ma_push_sp(Register r, AutoRegisterScope& scratch);
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void ma_vpop(VFPRegister r);
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void ma_vpush(VFPRegister r);
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// Barriers.
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void ma_dmb(BarrierOption option = BarrierSY);
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void ma_dsb(BarrierOption option = BarrierSY);
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// Branches when done from within arm-specific code.
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BufferOffset ma_b(Label* dest, Condition c = Always);
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void ma_b(void* target, Condition c = Always);
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void ma_bx(Register dest, Condition c = Always);
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// This is almost NEVER necessary, we'll basically never be calling a label
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// except, possibly in the crazy bailout-table case.
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void ma_bl(Label* dest, Condition c = Always);
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void ma_blx(Register dest, Condition c = Always);
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// VFP/ALU:
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void ma_vadd(FloatRegister src1, FloatRegister src2, FloatRegister dst);
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void ma_vsub(FloatRegister src1, FloatRegister src2, FloatRegister dst);
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void ma_vmul(FloatRegister src1, FloatRegister src2, FloatRegister dst);
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void ma_vdiv(FloatRegister src1, FloatRegister src2, FloatRegister dst);
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void ma_vneg(FloatRegister src, FloatRegister dest, Condition cc = Always);
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void ma_vmov(FloatRegister src, FloatRegister dest, Condition cc = Always);
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void ma_vmov_f32(FloatRegister src, FloatRegister dest,
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Condition cc = Always);
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void ma_vabs(FloatRegister src, FloatRegister dest, Condition cc = Always);
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void ma_vabs_f32(FloatRegister src, FloatRegister dest,
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Condition cc = Always);
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void ma_vsqrt(FloatRegister src, FloatRegister dest, Condition cc = Always);
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void ma_vsqrt_f32(FloatRegister src, FloatRegister dest,
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Condition cc = Always);
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void ma_vimm(double value, FloatRegister dest, Condition cc = Always);
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void ma_vimm_f32(float value, FloatRegister dest, Condition cc = Always);
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void ma_vcmp(FloatRegister src1, FloatRegister src2, Condition cc = Always);
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void ma_vcmp_f32(FloatRegister src1, FloatRegister src2,
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Condition cc = Always);
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void ma_vcmpz(FloatRegister src1, Condition cc = Always);
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void ma_vcmpz_f32(FloatRegister src1, Condition cc = Always);
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void ma_vadd_f32(FloatRegister src1, FloatRegister src2, FloatRegister dst);
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void ma_vsub_f32(FloatRegister src1, FloatRegister src2, FloatRegister dst);
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void ma_vmul_f32(FloatRegister src1, FloatRegister src2, FloatRegister dst);
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void ma_vdiv_f32(FloatRegister src1, FloatRegister src2, FloatRegister dst);
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void ma_vneg_f32(FloatRegister src, FloatRegister dest,
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Condition cc = Always);
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// Source is F64, dest is I32:
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void ma_vcvt_F64_I32(FloatRegister src, FloatRegister dest,
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Condition cc = Always);
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void ma_vcvt_F64_U32(FloatRegister src, FloatRegister dest,
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Condition cc = Always);
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// Source is I32, dest is F64:
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void ma_vcvt_I32_F64(FloatRegister src, FloatRegister dest,
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Condition cc = Always);
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void ma_vcvt_U32_F64(FloatRegister src, FloatRegister dest,
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Condition cc = Always);
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// Source is F32, dest is I32:
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void ma_vcvt_F32_I32(FloatRegister src, FloatRegister dest,
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Condition cc = Always);
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void ma_vcvt_F32_U32(FloatRegister src, FloatRegister dest,
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Condition cc = Always);
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// Source is I32, dest is F32:
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void ma_vcvt_I32_F32(FloatRegister src, FloatRegister dest,
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Condition cc = Always);
485
void ma_vcvt_U32_F32(FloatRegister src, FloatRegister dest,
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Condition cc = Always);
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// Transfer (do not coerce) a float into a gpr.
489
void ma_vxfer(VFPRegister src, Register dest, Condition cc = Always);
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// Transfer (do not coerce) a double into a couple of gpr.
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void ma_vxfer(VFPRegister src, Register dest1, Register dest2,
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Condition cc = Always);
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// Transfer (do not coerce) a gpr into a float
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void ma_vxfer(Register src, FloatRegister dest, Condition cc = Always);
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// Transfer (do not coerce) a couple of gpr into a double
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void ma_vxfer(Register src1, Register src2, FloatRegister dest,
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Condition cc = Always);
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500
BufferOffset ma_vdtr(LoadStore ls, const Address& addr, VFPRegister dest,
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AutoRegisterScope& scratch, Condition cc = Always);
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BufferOffset ma_vldr(VFPAddr addr, VFPRegister dest, Condition cc = Always);
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BufferOffset ma_vldr(const Address& addr, VFPRegister dest,
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AutoRegisterScope& scratch, Condition cc = Always);
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BufferOffset ma_vldr(VFPRegister src, Register base, Register index,
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AutoRegisterScope& scratch, int32_t shift = defaultShift,
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Condition cc = Always);
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BufferOffset ma_vstr(VFPRegister src, VFPAddr addr, Condition cc = Always);
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BufferOffset ma_vstr(VFPRegister src, const Address& addr,
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AutoRegisterScope& scratch, Condition cc = Always);
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BufferOffset ma_vstr(VFPRegister src, Register base, Register index,
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AutoRegisterScope& scratch, AutoRegisterScope& scratch2,
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int32_t shift, int32_t offset, Condition cc = Always);
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BufferOffset ma_vstr(VFPRegister src, Register base, Register index,
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AutoRegisterScope& scratch, int32_t shift,
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Condition cc = Always);
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void ma_call(ImmPtr dest);
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// Float registers can only be loaded/stored in continuous runs when using
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// vstm/vldm. This function breaks set into continuous runs and loads/stores
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// them at [rm]. rm will be modified and left in a state logically suitable
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// for the next load/store. Returns the offset from [dm] for the logical
526
// next load/store.
527
int32_t transferMultipleByRuns(FloatRegisterSet set, LoadStore ls,
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Register rm, DTMMode mode) {
529
if (mode == IA) {
530
return transferMultipleByRunsImpl<FloatRegisterForwardIterator>(
531
set, ls, rm, mode, 1);
532
}
533
if (mode == DB) {
534
return transferMultipleByRunsImpl<FloatRegisterBackwardIterator>(
535
set, ls, rm, mode, -1);
536
}
537
MOZ_CRASH("Invalid data transfer addressing mode");
538
}
539
540
// `outAny` is valid if and only if `out64` == Register64::Invalid().
541
void wasmLoadImpl(const wasm::MemoryAccessDesc& access, Register memoryBase,
542
Register ptr, Register ptrScratch, AnyRegister outAny,
543
Register64 out64);
544
545
// `valAny` is valid if and only if `val64` == Register64::Invalid().
546
void wasmStoreImpl(const wasm::MemoryAccessDesc& access, AnyRegister valAny,
547
Register64 val64, Register memoryBase, Register ptr,
548
Register ptrScratch);
549
550
protected:
551
// `outAny` is valid if and only if `out64` == Register64::Invalid().
552
void wasmUnalignedLoadImpl(const wasm::MemoryAccessDesc& access,
553
Register memoryBase, Register ptr,
554
Register ptrScratch, AnyRegister outAny,
555
Register64 out64, Register tmp1, Register tmp2,
556
Register tmp3);
557
558
// The value to be stored is in `floatValue` (if not invalid), `val64` (if not
559
// invalid), or in `valOrTmp` (if `floatValue` and `val64` are both invalid).
560
// Note `valOrTmp` must always be valid.
561
void wasmUnalignedStoreImpl(const wasm::MemoryAccessDesc& access,
562
FloatRegister floatValue, Register64 val64,
563
Register memoryBase, Register ptr,
564
Register ptrScratch, Register valOrTmp);
565
566
private:
567
// Loads `byteSize` bytes, byte by byte, by reading from ptr[offset],
568
// applying the indicated signedness (defined by isSigned).
569
// - all three registers must be different.
570
// - tmp and dest will get clobbered, ptr will remain intact.
571
// - byteSize can be up to 4 bytes and no more (GPR are 32 bits on ARM).
572
// - offset can be 0 or 4
573
// If `access` is not null then emit the appropriate access metadata.
574
void emitUnalignedLoad(const wasm::MemoryAccessDesc* access, bool isSigned,
575
unsigned byteSize, Register ptr, Register tmp,
576
Register dest, unsigned offset = 0);
577
578
// Ditto, for a store. Note stores don't care about signedness.
579
// - the two registers must be different.
580
// - val will get clobbered, ptr will remain intact.
581
// - byteSize can be up to 4 bytes and no more (GPR are 32 bits on ARM).
582
// - offset can be 0 or 4
583
// If `access` is not null then emit the appropriate access metadata.
584
void emitUnalignedStore(const wasm::MemoryAccessDesc* access,
585
unsigned byteSize, Register ptr, Register val,
586
unsigned offset = 0);
587
588
// Implementation for transferMultipleByRuns so we can use different
589
// iterators for forward/backward traversals. The sign argument should be 1
590
// if we traverse forwards, -1 if we traverse backwards.
591
template <typename RegisterIterator>
592
int32_t transferMultipleByRunsImpl(FloatRegisterSet set, LoadStore ls,
593
Register rm, DTMMode mode, int32_t sign) {
594
MOZ_ASSERT(sign == 1 || sign == -1);
595
596
int32_t delta = sign * sizeof(float);
597
int32_t offset = 0;
598
// Build up a new set, which is the sum of all of the single and double
599
// registers. This set can have up to 48 registers in it total
600
// s0-s31 and d16-d31
601
FloatRegisterSet mod = set.reduceSetForPush();
602
603
RegisterIterator iter(mod);
604
while (iter.more()) {
605
startFloatTransferM(ls, rm, mode, WriteBack);
606
int32_t reg = (*iter).code();
607
do {
608
offset += delta;
609
if ((*iter).isDouble()) {
610
offset += delta;
611
}
612
transferFloatReg(*iter);
613
} while ((++iter).more() && int32_t((*iter).code()) == (reg += sign));
614
finishFloatTransfer();
615
}
616
return offset;
617
}
618
};
619
620
class MacroAssembler;
621
622
class MacroAssemblerARMCompat : public MacroAssemblerARM {
623
private:
624
// Perform a downcast. Should be removed by Bug 996602.
625
MacroAssembler& asMasm();
626
const MacroAssembler& asMasm() const;
627
628
public:
629
MacroAssemblerARMCompat() {}
630
631
public:
632
// Jumps + other functions that should be called from non-arm specific
633
// code. Basically, an x86 front end on top of the ARM code.
634
void j(Condition code, Label* dest) { as_b(dest, code); }
635
void j(Label* dest) { as_b(dest, Always); }
636
637
void mov(Register src, Register dest) { ma_mov(src, dest); }
638
void mov(ImmWord imm, Register dest) { ma_mov(Imm32(imm.value), dest); }
639
void mov(ImmPtr imm, Register dest) {
640
mov(ImmWord(uintptr_t(imm.value)), dest);
641
}
642
643
void branch(JitCode* c) {
644
BufferOffset bo = m_buffer.nextOffset();
645
addPendingJump(bo, ImmPtr(c->raw()), RelocationKind::JITCODE);
646
ScratchRegisterScope scratch(asMasm());
647
ma_movPatchable(ImmPtr(c->raw()), scratch, Always);
648
ma_bx(scratch);
649
}
650
void branch(const Register reg) { ma_bx(reg); }
651
void nop() { ma_nop(); }
652
void shortJumpSizedNop() { ma_nop(); }
653
void ret() { ma_pop(pc); }
654
void retn(Imm32 n) {
655
ScratchRegisterScope scratch(asMasm());
656
SecondScratchRegisterScope scratch2(asMasm());
657
ma_popn_pc(n, scratch, scratch2);
658
}
659
void push(Imm32 imm) {
660
ScratchRegisterScope scratch(asMasm());
661
ma_mov(imm, scratch);
662
ma_push(scratch);
663
}
664
void push(ImmWord imm) { push(Imm32(imm.value)); }
665
void push(ImmGCPtr imm) {
666
ScratchRegisterScope scratch(asMasm());
667
ma_mov(imm, scratch);
668
ma_push(scratch);
669
}
670
void push(const Address& addr) {
671
ScratchRegisterScope scratch(asMasm());
672
SecondScratchRegisterScope scratch2(asMasm());
673
ma_ldr(addr, scratch, scratch2);
674
ma_push(scratch);
675
}
676
void push(Register reg) {
677
if (reg == sp) {
678
ScratchRegisterScope scratch(asMasm());
679
ma_push_sp(reg, scratch);
680
} else {
681
ma_push(reg);
682
}
683
}
684
void push(FloatRegister reg) { ma_vpush(VFPRegister(reg)); }
685
void pushWithPadding(Register reg, const Imm32 extraSpace) {
686
ScratchRegisterScope scratch(asMasm());
687
Imm32 totSpace = Imm32(extraSpace.value + 4);
688
ma_dtr(IsStore, sp, totSpace, reg, scratch, PreIndex);
689
}
690
void pushWithPadding(Imm32 imm, const Imm32 extraSpace) {
691
ScratchRegisterScope scratch(asMasm());
692
SecondScratchRegisterScope scratch2(asMasm());
693
Imm32 totSpace = Imm32(extraSpace.value + 4);
694
ma_mov(imm, scratch);
695
ma_dtr(IsStore, sp, totSpace, scratch, scratch2, PreIndex);
696
}
697
698
void pop(Register reg) { ma_pop(reg); }
699
void pop(FloatRegister reg) { ma_vpop(VFPRegister(reg)); }
700
701
void popN(Register reg, Imm32 extraSpace) {
702
ScratchRegisterScope scratch(asMasm());
703
Imm32 totSpace = Imm32(extraSpace.value + 4);
704
ma_dtr(IsLoad, sp, totSpace, reg, scratch, PostIndex);
705
}
706
707
CodeOffset toggledJump(Label* label);
708
709
// Emit a BLX or NOP instruction. ToggleCall can be used to patch this
710
// instruction.
711
CodeOffset toggledCall(JitCode* target, bool enabled);
712
713
CodeOffset pushWithPatch(ImmWord imm) {
714
ScratchRegisterScope scratch(asMasm());
715
CodeOffset label = movWithPatch(imm, scratch);
716
ma_push(scratch);
717
return label;
718
}
719
720
CodeOffset movWithPatch(ImmWord imm, Register dest) {
721
CodeOffset label = CodeOffset(currentOffset());
722
ma_movPatchable(Imm32(imm.value), dest, Always);
723
return label;
724
}
725
CodeOffset movWithPatch(ImmPtr imm, Register dest) {
726
return movWithPatch(ImmWord(uintptr_t(imm.value)), dest);
727
}
728
729
void jump(Label* label) { as_b(label); }
730
void jump(JitCode* code) { branch(code); }
731
void jump(ImmPtr ptr) {
732
ScratchRegisterScope scratch(asMasm());
733
movePtr(ptr, scratch);
734
ma_bx(scratch);
735
}
736
void jump(TrampolinePtr code) { jump(ImmPtr(code.value)); }
737
void jump(Register reg) { ma_bx(reg); }
738
void jump(const Address& addr) {
739
ScratchRegisterScope scratch(asMasm());
740
SecondScratchRegisterScope scratch2(asMasm());
741
ma_ldr(addr, scratch, scratch2);
742
ma_bx(scratch);
743
}
744
745
void negl(Register reg) { ma_neg(reg, reg, SetCC); }
746
void test32(Register lhs, Register rhs) { ma_tst(lhs, rhs); }
747
void test32(Register lhs, Imm32 imm) {
748
ScratchRegisterScope scratch(asMasm());
749
ma_tst(lhs, imm, scratch);
750
}
751
void test32(const Address& addr, Imm32 imm) {
752
ScratchRegisterScope scratch(asMasm());
753
SecondScratchRegisterScope scratch2(asMasm());
754
ma_ldr(addr, scratch, scratch2);
755
ma_tst(scratch, imm, scratch2);
756
}
757
void testPtr(Register lhs, Register rhs) { test32(lhs, rhs); }
758
759
void splitTagForTest(const ValueOperand& value, ScratchTagScope& tag) {
760
MOZ_ASSERT(value.typeReg() == tag);
761
}
762
763
// Higher level tag testing code.
764
Condition testInt32(Condition cond, const ValueOperand& value);
765
Condition testBoolean(Condition cond, const ValueOperand& value);
766
Condition testDouble(Condition cond, const ValueOperand& value);
767
Condition testNull(Condition cond, const ValueOperand& value);
768
Condition testUndefined(Condition cond, const ValueOperand& value);
769
Condition testString(Condition cond, const ValueOperand& value);
770
Condition testSymbol(Condition cond, const ValueOperand& value);
771
Condition testBigInt(Condition cond, const ValueOperand& value);
772
Condition testObject(Condition cond, const ValueOperand& value);
773
Condition testNumber(Condition cond, const ValueOperand& value);
774
Condition testMagic(Condition cond, const ValueOperand& value);
775
776
Condition testPrimitive(Condition cond, const ValueOperand& value);
777
778
// Register-based tests.
779
Condition testInt32(Condition cond, Register tag);
780
Condition testBoolean(Condition cond, Register tag);
781
Condition testNull(Condition cond, Register tag);
782
Condition testUndefined(Condition cond, Register tag);
783
Condition testString(Condition cond, Register tag);
784
Condition testSymbol(Condition cond, Register tag);
785
Condition testBigInt(Condition cond, Register tag);
786
Condition testObject(Condition cond, Register tag);
787
Condition testDouble(Condition cond, Register tag);
788
Condition testNumber(Condition cond, Register tag);
789
Condition testMagic(Condition cond, Register tag);
790
Condition testPrimitive(Condition cond, Register tag);
791
792
Condition testGCThing(Condition cond, const Address& address);
793
Condition testMagic(Condition cond, const Address& address);
794
Condition testInt32(Condition cond, const Address& address);
795
Condition testDouble(Condition cond, const Address& address);
796
Condition testBoolean(Condition cond, const Address& address);
797
Condition testNull(Condition cond, const Address& address);
798
Condition testUndefined(Condition cond, const Address& address);
799
Condition testString(Condition cond, const Address& address);
800
Condition testSymbol(Condition cond, const Address& address);
801
Condition testBigInt(Condition cond, const Address& address);
802
Condition testObject(Condition cond, const Address& address);
803
Condition testNumber(Condition cond, const Address& address);
804
805
Condition testUndefined(Condition cond, const BaseIndex& src);
806
Condition testNull(Condition cond, const BaseIndex& src);
807
Condition testBoolean(Condition cond, const BaseIndex& src);
808
Condition testString(Condition cond, const BaseIndex& src);
809
Condition testSymbol(Condition cond, const BaseIndex& src);
810
Condition testBigInt(Condition cond, const BaseIndex& src);
811
Condition testInt32(Condition cond, const BaseIndex& src);
812
Condition testObject(Condition cond, const BaseIndex& src);
813
Condition testDouble(Condition cond, const BaseIndex& src);
814
Condition testMagic(Condition cond, const BaseIndex& src);
815
Condition testGCThing(Condition cond, const BaseIndex& src);
816
817
// Unboxing code.
818
void unboxNonDouble(const ValueOperand& operand, Register dest,
819
JSValueType type);
820
void unboxNonDouble(const Address& src, Register dest, JSValueType type);
821
void unboxNonDouble(const BaseIndex& src, Register dest, JSValueType type);
822
void unboxInt32(const ValueOperand& src, Register dest) {
823
unboxNonDouble(src, dest, JSVAL_TYPE_INT32);
824
}
825
void unboxInt32(const Address& src, Register dest) {
826
unboxNonDouble(src, dest, JSVAL_TYPE_INT32);
827
}
828
void unboxBoolean(const ValueOperand& src, Register dest) {
829
unboxNonDouble(src, dest, JSVAL_TYPE_BOOLEAN);
830
}
831
void unboxBoolean(const Address& src, Register dest) {
832
unboxNonDouble(src, dest, JSVAL_TYPE_BOOLEAN);
833
}
834
void unboxString(const ValueOperand& src, Register dest) {
835
unboxNonDouble(src, dest, JSVAL_TYPE_STRING);
836
}
837
void unboxString(const Address& src, Register dest) {
838
unboxNonDouble(src, dest, JSVAL_TYPE_STRING);
839
}
840
void unboxSymbol(const ValueOperand& src, Register dest) {
841
unboxNonDouble(src, dest, JSVAL_TYPE_SYMBOL);
842
}
843
void unboxSymbol(const Address& src, Register dest) {
844
unboxNonDouble(src, dest, JSVAL_TYPE_SYMBOL);
845
}
846
void unboxBigInt(const ValueOperand& src, Register dest) {
847
unboxNonDouble(src, dest, JSVAL_TYPE_BIGINT);
848
}
849
void unboxBigInt(const Address& src, Register dest) {
850
unboxNonDouble(src, dest, JSVAL_TYPE_BIGINT);
851
}
852
void unboxObject(const ValueOperand& src, Register dest) {
853
unboxNonDouble(src, dest, JSVAL_TYPE_OBJECT);
854
}
855
void unboxObject(const Address& src, Register dest) {
856
unboxNonDouble(src, dest, JSVAL_TYPE_OBJECT);
857
}
858
void unboxObject(const BaseIndex& src, Register dest) {
859
unboxNonDouble(src, dest, JSVAL_TYPE_OBJECT);
860
}
861
void unboxDouble(const ValueOperand& src, FloatRegister dest);
862
void unboxDouble(const Address& src, FloatRegister dest);
863
void unboxDouble(const BaseIndex& src, FloatRegister dest);
864
865
void unboxValue(const ValueOperand& src, AnyRegister dest, JSValueType type);
866
867
// See comment in MacroAssembler-x64.h.
868
void unboxGCThingForPreBarrierTrampoline(const Address& src, Register dest) {
869
load32(ToPayload(src), dest);
870
}
871
872
void notBoolean(const ValueOperand& val) {
873
as_eor(val.payloadReg(), val.payloadReg(), Imm8(1));
874
}
875
876
// Boxing code.
877
void boxDouble(FloatRegister src, const ValueOperand& dest, FloatRegister);
878
void boxNonDouble(JSValueType type, Register src, const ValueOperand& dest);
879
880
// Extended unboxing API. If the payload is already in a register, returns
881
// that register. Otherwise, provides a move to the given scratch register,
882
// and returns that.
883
MOZ_MUST_USE Register extractObject(const Address& address, Register scratch);
884
MOZ_MUST_USE Register extractObject(const ValueOperand& value,
885
Register scratch) {
886
unboxNonDouble(value, value.payloadReg(), JSVAL_TYPE_OBJECT);
887
return value.payloadReg();
888
}
889
MOZ_MUST_USE Register extractSymbol(const ValueOperand& value,
890
Register scratch) {
891
unboxNonDouble(value, value.payloadReg(), JSVAL_TYPE_SYMBOL);
892
return value.payloadReg();
893
}
894
MOZ_MUST_USE Register extractInt32(const ValueOperand& value,
895
Register scratch) {
896
return value.payloadReg();
897
}
898
MOZ_MUST_USE Register extractBoolean(const ValueOperand& value,
899
Register scratch) {
900
return value.payloadReg();
901
}
902
MOZ_MUST_USE Register extractTag(const Address& address, Register scratch);
903
MOZ_MUST_USE Register extractTag(const BaseIndex& address, Register scratch);
904
MOZ_MUST_USE Register extractTag(const ValueOperand& value,
905
Register scratch) {
906
return value.typeReg();
907
}
908
909
void boolValueToDouble(const ValueOperand& operand, FloatRegister dest);
910
void int32ValueToDouble(const ValueOperand& operand, FloatRegister dest);
911
void loadInt32OrDouble(const Address& src, FloatRegister dest);
912
void loadInt32OrDouble(Register base, Register index, FloatRegister dest,
913
int32_t shift = defaultShift);
914
void loadConstantDouble(double dp, FloatRegister dest);
915
916
// Treat the value as a boolean, and set condition codes accordingly.
917
Condition testInt32Truthy(bool truthy, const ValueOperand& operand);
918
Condition testBooleanTruthy(bool truthy, const ValueOperand& operand);
919
Condition testDoubleTruthy(bool truthy, FloatRegister reg);
920
Condition testStringTruthy(bool truthy, const ValueOperand& value);
921
Condition testBigIntTruthy(bool truthy, const ValueOperand& value);
922
923
void boolValueToFloat32(const ValueOperand& operand, FloatRegister dest);
924
void int32ValueToFloat32(const ValueOperand& operand, FloatRegister dest);
925
void loadConstantFloat32(float f, FloatRegister dest);
926
927
void loadUnboxedValue(Address address, MIRType type, AnyRegister dest) {
928
if (dest.isFloat()) {
929
loadInt32OrDouble(address, dest.fpu());
930
} else {
931
ScratchRegisterScope scratch(asMasm());
932
ma_ldr(address, dest.gpr(), scratch);
933
}
934
}
935
936
void loadUnboxedValue(BaseIndex address, MIRType type, AnyRegister dest) {
937
if (dest.isFloat()) {
938
loadInt32OrDouble(address.base, address.index, dest.fpu(), address.scale);
939
} else {
940
load32(address, dest.gpr());
941
}
942
}
943
944
template <typename T>
945
void storeUnboxedPayload(ValueOperand value, T address, size_t nbytes,
946
JSValueType) {
947
switch (nbytes) {
948
case 4:
949
storePtr(value.payloadReg(), address);
950
return;
951
case 1:
952
store8(value.payloadReg(), address);
953
return;
954
default:
955
MOZ_CRASH("Bad payload width");
956
}
957
}
958
959
void storeValue(ValueOperand val, const Address& dst);
960
void storeValue(ValueOperand val, const BaseIndex& dest);
961
void storeValue(JSValueType type, Register reg, BaseIndex dest) {
962
ScratchRegisterScope scratch(asMasm());
963
SecondScratchRegisterScope scratch2(asMasm());
964
965
int32_t payloadoffset = dest.offset + NUNBOX32_PAYLOAD_OFFSET;
966
int32_t typeoffset = dest.offset + NUNBOX32_TYPE_OFFSET;
967
968
ma_alu(dest.base, lsl(dest.index, dest.scale), scratch, OpAdd);
969
970
// Store the payload.
971
if (payloadoffset < 4096 && payloadoffset > -4096) {
972
ma_str(reg, DTRAddr(scratch, DtrOffImm(payloadoffset)));
973
} else {
974
ma_str(reg, Address(scratch, payloadoffset), scratch2);
975
}
976
977
// Store the type.
978
if (typeoffset < 4096 && typeoffset > -4096) {
979
// Encodable as DTRAddr, so only two instructions needed.
980
ma_mov(ImmTag(JSVAL_TYPE_TO_TAG(type)), scratch2);
981
ma_str(scratch2, DTRAddr(scratch, DtrOffImm(typeoffset)));
982
} else {
983
// Since there are only two scratch registers, the offset must be
984
// applied early using a third instruction to be safe.
985
ma_add(Imm32(typeoffset), scratch, scratch2);
986
ma_mov(ImmTag(JSVAL_TYPE_TO_TAG(type)), scratch2);
987
ma_str(scratch2, DTRAddr(scratch, DtrOffImm(0)));
988
}
989
}
990
void storeValue(JSValueType type, Register reg, Address dest) {
991
ScratchRegisterScope scratch(asMasm());
992
SecondScratchRegisterScope scratch2(asMasm());
993
994
ma_str(reg, dest, scratch2);
995
ma_mov(ImmTag(JSVAL_TYPE_TO_TAG(type)), scratch);
996
ma_str(scratch, Address(dest.base, dest.offset + NUNBOX32_TYPE_OFFSET),
997
scratch2);
998
}
999
void storeValue(const Value& val, const Address& dest) {
1000
ScratchRegisterScope scratch(asMasm());
1001
SecondScratchRegisterScope scratch2(asMasm());
1002
1003
ma_mov(Imm32(val.toNunboxTag()), scratch);
1004
ma_str(scratch, ToType(dest), scratch2);
1005
if (val.isGCThing()) {
1006
ma_mov(ImmGCPtr(val.toGCThing()), scratch);
1007
} else {
1008
ma_mov(Imm32(val.toNunboxPayload()), scratch);
1009
}
1010
ma_str(scratch, ToPayload(dest), scratch2);
1011
}
1012
void storeValue(const Value& val, BaseIndex dest) {
1013
ScratchRegisterScope scratch(asMasm());
1014
SecondScratchRegisterScope scratch2(asMasm());
1015
1016
int32_t typeoffset = dest.offset + NUNBOX32_TYPE_OFFSET;
1017
int32_t payloadoffset = dest.offset + NUNBOX32_PAYLOAD_OFFSET;
1018
1019
ma_alu(dest.base, lsl(dest.index, dest.scale), scratch, OpAdd);
1020
1021
// Store the type.
1022
if (typeoffset < 4096 && typeoffset > -4096) {
1023
ma_mov(Imm32(val.toNunboxTag()), scratch2);
1024
ma_str(scratch2, DTRAddr(scratch, DtrOffImm(typeoffset)));
1025
} else {
1026
ma_add(Imm32(typeoffset), scratch, scratch2);
1027
ma_mov(Imm32(val.toNunboxTag()), scratch2);
1028
ma_str(scratch2, DTRAddr(scratch, DtrOffImm(0)));
1029
// Restore scratch for the payload store.
1030
ma_alu(dest.base, lsl(dest.index, dest.scale), scratch, OpAdd);
1031
}
1032
1033
// Store the payload, marking if necessary.
1034
if (payloadoffset < 4096 && payloadoffset > -4096) {
1035
if (val.isGCThing()) {
1036
ma_mov(ImmGCPtr(val.toGCThing()), scratch2);
1037
} else {
1038
ma_mov(Imm32(val.toNunboxPayload()), scratch2);
1039
}
1040
ma_str(scratch2, DTRAddr(scratch, DtrOffImm(payloadoffset)));
1041
} else {
1042
ma_add(Imm32(payloadoffset), scratch, scratch2);
1043
if (val.isGCThing()) {
1044
ma_mov(ImmGCPtr(val.toGCThing()), scratch2);
1045
} else {
1046
ma_mov(Imm32(val.toNunboxPayload()), scratch2);
1047
}
1048
ma_str(scratch2, DTRAddr(scratch, DtrOffImm(0)));
1049
}
1050
}
1051
void storeValue(const Address& src, const Address& dest, Register temp) {
1052
load32(ToType(src), temp);
1053
store32(temp, ToType(dest));
1054
1055
load32(ToPayload(src), temp);
1056
store32(temp, ToPayload(dest));
1057
}
1058
1059
void loadValue(Address src, ValueOperand val);
1060
void loadValue(Operand dest, ValueOperand val) {
1061
loadValue(dest.toAddress(), val);
1062
}
1063
void loadValue(const BaseIndex& addr, ValueOperand val);
1064
1065
// Like loadValue but guaranteed to not use LDRD or LDM instructions (these
1066
// don't support unaligned accesses).
1067
void loadUnalignedValue(const Address& src, ValueOperand dest);
1068
1069
void tagValue(JSValueType type, Register payload, ValueOperand dest);
1070
1071
void pushValue(ValueOperand val);
1072
void popValue(ValueOperand val);
1073
void pushValue(const Value& val) {
1074
push(Imm32(val.toNunboxTag()));
1075
if (val.isGCThing()) {
1076
push(ImmGCPtr(val.toGCThing()));
1077
} else {
1078
push(Imm32(val.toNunboxPayload()));
1079
}
1080
}
1081
void pushValue(JSValueType type, Register reg) {
1082
push(ImmTag(JSVAL_TYPE_TO_TAG(type)));
1083
ma_push(reg);
1084
}
1085
void pushValue(const Address& addr);
1086
1087
void storePayload(const Value& val, const Address& dest);
1088
void storePayload(Register src, const Address& dest);
1089
void storePayload(const Value& val, const BaseIndex& dest);
1090
void storePayload(Register src, const BaseIndex& dest);
1091
void storeTypeTag(ImmTag tag, const Address& dest);
1092
void storeTypeTag(ImmTag tag, const BaseIndex& dest);
1093
1094
void handleFailureWithHandlerTail(void* handler, Label* profilerExitTail);
1095
1096
/////////////////////////////////////////////////////////////////
1097
// Common interface.
1098
/////////////////////////////////////////////////////////////////
1099
public:
1100
void not32(Register reg);
1101
1102
void move32(Imm32 imm, Register dest);
1103
void move32(Register src, Register dest);
1104
1105
void movePtr(Register src, Register dest);
1106
void movePtr(ImmWord imm, Register dest);
1107
void movePtr(ImmPtr imm, Register dest);
1108
void movePtr(wasm::SymbolicAddress imm, Register dest);
1109
void movePtr(ImmGCPtr imm, Register dest);
1110
1111
void load8SignExtend(const Address& address, Register dest);
1112
void load8SignExtend(const BaseIndex& src, Register dest);
1113
1114
void load8ZeroExtend(const Address& address, Register dest);
1115
void load8ZeroExtend(const BaseIndex& src, Register dest);
1116
1117
void load16SignExtend(const Address& address, Register dest);
1118
void load16SignExtend(const BaseIndex& src, Register dest);
1119
1120
void load16ZeroExtend(const Address& address, Register dest);
1121
void load16ZeroExtend(const BaseIndex& src, Register dest);
1122
1123
void load32(const Address& address, Register dest);
1124
void load32(const BaseIndex& address, Register dest);
1125
void load32(AbsoluteAddress address, Register dest);
1126
void load64(const Address& address, Register64 dest) {
1127
load32(LowWord(address), dest.low);
1128
load32(HighWord(address), dest.high);
1129
}
1130
void load64(const BaseIndex& address, Register64 dest) {
1131
load32(LowWord(address), dest.low);
1132
load32(HighWord(address), dest.high);
1133
}
1134
1135
void loadPtr(const Address& address, Register dest);
1136
void loadPtr(const BaseIndex& src, Register dest);
1137
void loadPtr(AbsoluteAddress address, Register dest);
1138
void loadPtr(wasm::SymbolicAddress address, Register dest);
1139
1140
void loadPrivate(const Address& address, Register dest);
1141
1142
void loadDouble(const Address& addr, FloatRegister dest);
1143
void loadDouble(const BaseIndex& src, FloatRegister dest);
1144
1145
// Load a float value into a register, then expand it to a double.
1146
void loadFloatAsDouble(const Address& addr, FloatRegister dest);
1147
void loadFloatAsDouble(const BaseIndex& src, FloatRegister dest);
1148
1149
void loadFloat32(const Address& addr, FloatRegister dest);
1150
void loadFloat32(const BaseIndex& src, FloatRegister dest);
1151
1152
void store8(Register src, const Address& address);
1153
void store8(Imm32 imm, const Address& address);
1154
void store8(Register src, const BaseIndex& address);
1155
void store8(Imm32 imm, const BaseIndex& address);
1156
1157
void store16(Register src, const Address& address);
1158
void store16(Imm32 imm, const Address& address);
1159
void store16(Register src, const BaseIndex& address);
1160
void store16(Imm32 imm, const BaseIndex& address);
1161
1162
void store32(Register src, AbsoluteAddress address);
1163
void store32(Register src, const Address& address);
1164
void store32(Register src, const BaseIndex& address);
1165
void store32(Imm32 src, const Address& address);
1166
void store32(Imm32 src, const BaseIndex& address);
1167
1168
void store64(Register64 src, Address address) {
1169
store32(src.low, LowWord(address));
1170
store32(src.high, HighWord(address));
1171
}
1172
1173
void store64(Register64 src, const BaseIndex& address) {
1174
store32(src.low, LowWord(address));
1175
store32(src.high, HighWord(address));
1176
}
1177
1178
void store64(Imm64 imm, Address address) {
1179
store32(imm.low(), LowWord(address));
1180
store32(imm.hi(), HighWord(address));
1181
}
1182
1183
void store64(Imm64 imm, const BaseIndex& address) {
1184
store32(imm.low(), LowWord(address));
1185
store32(imm.hi(), HighWord(address));
1186
}
1187
1188
void storePtr(ImmWord imm, const Address& address);
1189
void storePtr(ImmWord imm, const BaseIndex& address);
1190
void storePtr(ImmPtr imm, const Address& address);
1191
void storePtr(ImmPtr imm, const BaseIndex& address);
1192
void storePtr(ImmGCPtr imm, const Address& address);
1193
void storePtr(ImmGCPtr imm, const BaseIndex& address);
1194
void storePtr(Register src, const Address& address);
1195
void storePtr(Register src, const BaseIndex& address);
1196
void storePtr(Register src, AbsoluteAddress dest);
1197
1198
void moveDouble(FloatRegister src, FloatRegister dest,
1199
Condition cc = Always) {
1200
ma_vmov(src, dest, cc);
1201
}
1202
1203
inline void incrementInt32Value(const Address& addr);
1204
1205
void cmp32(Register lhs, Imm32 rhs);
1206
void cmp32(Register lhs, Register rhs);
1207
void cmp32(const Address& lhs, Imm32 rhs);
1208
void cmp32(const Address& lhs, Register rhs);
1209
1210
void cmpPtr(Register lhs, Register rhs);
1211
void cmpPtr(Register lhs, ImmWord rhs);
1212
void cmpPtr(Register lhs, ImmPtr rhs);
1213
void cmpPtr(Register lhs, ImmGCPtr rhs);
1214
void cmpPtr(Register lhs, Imm32 rhs);
1215
void cmpPtr(const Address& lhs, Register rhs);
1216
void cmpPtr(const Address& lhs, ImmWord rhs);
1217
void cmpPtr(const Address& lhs, ImmPtr rhs);
1218
void cmpPtr(const Address& lhs, ImmGCPtr rhs);
1219
void cmpPtr(const Address& lhs, Imm32 rhs);
1220
1221
void setStackArg(Register reg, uint32_t arg);
1222
1223
void breakpoint();
1224
// Conditional breakpoint.
1225
void breakpoint(Condition cc);
1226
1227
// Trigger the simulator's interactive read-eval-print loop.
1228
// The message will be printed at the stopping point.
1229
// (On non-simulator builds, does nothing.)
1230
void simulatorStop(const char* msg);
1231
1232
// Evaluate srcDest = minmax<isMax>{Float32,Double}(srcDest, other).
1233
// Checks for NaN if canBeNaN is true.
1234
void minMaxDouble(FloatRegister srcDest, FloatRegister other, bool canBeNaN,
1235
bool isMax);
1236
void minMaxFloat32(FloatRegister srcDest, FloatRegister other, bool canBeNaN,
1237
bool isMax);
1238
1239
void compareDouble(FloatRegister lhs, FloatRegister rhs);
1240
1241
void compareFloat(FloatRegister lhs, FloatRegister rhs);
1242
1243
void checkStackAlignment();
1244
1245
// If source is a double, load it into dest. If source is int32, convert it
1246
// to double. Else, branch to failure.
1247
void ensureDouble(const ValueOperand& source, FloatRegister dest,
1248
Label* failure);
1249
1250
void emitSet(Assembler::Condition cond, Register dest) {
1251
ma_mov(Imm32(0), dest);
1252
ma_mov(Imm32(1), dest, cond);
1253
}
1254
1255
void testNullSet(Condition cond, const ValueOperand& value, Register dest) {
1256
cond = testNull(cond, value);
1257
emitSet(cond, dest);
1258
}
1259
1260
void testObjectSet(Condition cond, const ValueOperand& value, Register dest) {
1261
cond = testObject(cond, value);
1262
emitSet(cond, dest);
1263
}
1264
1265
void testUndefinedSet(Condition cond, const ValueOperand& value,
1266
Register dest) {
1267
cond = testUndefined(cond, value);
1268
emitSet(cond, dest);
1269
}
1270
1271
protected:
1272
bool buildOOLFakeExitFrame(void* fakeReturnAddr);
1273
1274
public:
1275
void computeEffectiveAddress(const Address& address, Register dest) {
1276
ScratchRegisterScope scratch(asMasm());
1277
ma_add(address.base, Imm32(address.offset), dest, scratch, LeaveCC);
1278
}
1279
void computeEffectiveAddress(const BaseIndex& address, Register dest) {
1280
ScratchRegisterScope scratch(asMasm());
1281
ma_alu(address.base, lsl(address.index, address.scale), dest, OpAdd,
1282
LeaveCC);
1283
if (address.offset) {
1284
ma_add(dest, Imm32(address.offset), dest, scratch, LeaveCC);
1285
}
1286
}
1287
void floor(FloatRegister input, Register output, Label* handleNotAnInt);
1288
void floorf(FloatRegister input, Register output, Label* handleNotAnInt);
1289
void ceil(FloatRegister input, Register output, Label* handleNotAnInt);
1290
void ceilf(FloatRegister input, Register output, Label* handleNotAnInt);
1291
void round(FloatRegister input, Register output, Label* handleNotAnInt,
1292
FloatRegister tmp);
1293
void roundf(FloatRegister input, Register output, Label* handleNotAnInt,
1294
FloatRegister tmp);
1295
void trunc(FloatRegister input, Register output, Label* handleNotAnInt);
1296
void truncf(FloatRegister input, Register output, Label* handleNotAnInt);
1297
1298
void clampCheck(Register r, Label* handleNotAnInt) {
1299
// Check explicitly for r == INT_MIN || r == INT_MAX
1300
// This is the instruction sequence that gcc generated for this
1301
// operation.
1302
ScratchRegisterScope scratch(asMasm());
1303
SecondScratchRegisterScope scratch2(asMasm());
1304
ma_sub(r, Imm32(0x80000001), scratch, scratch2);
1305
as_cmn(scratch, Imm8(3));
1306
ma_b(handleNotAnInt, Above);
1307
}
1308
1309
void lea(Operand addr, Register dest) {
1310
ScratchRegisterScope scratch(asMasm());
1311
ma_add(addr.baseReg(), Imm32(addr.disp()), dest, scratch);
1312
}
1313
1314
void abiret() { as_bx(lr); }
1315
1316
void moveFloat32(FloatRegister src, FloatRegister dest,
1317
Condition cc = Always) {
1318
as_vmov(VFPRegister(dest).singleOverlay(), VFPRegister(src).singleOverlay(),
1319
cc);
1320
}
1321
1322
void loadWasmGlobalPtr(uint32_t globalDataOffset, Register dest) {
1323
loadPtr(Address(WasmTlsReg,
1324
offsetof(wasm::TlsData, globalArea) + globalDataOffset),
1325
dest);
1326
}
1327
void loadWasmPinnedRegsFromTls() {
1328
ScratchRegisterScope scratch(asMasm());
1329
ma_ldr(Address(WasmTlsReg, offsetof(wasm::TlsData, memoryBase)), HeapReg,
1330
scratch);
1331
}
1332
1333
// Instrumentation for entering and leaving the profiler.
1334
void profilerEnterFrame(Register framePtr, Register scratch);
1335
void profilerExitFrame();
1336
};
1337
1338
typedef MacroAssemblerARMCompat MacroAssemblerSpecific;
1339
1340
} // namespace jit
1341
} // namespace js
1342
1343
#endif /* jit_arm_MacroAssembler_arm_h */