Source code

Revision control

Other Tools

#if 0
//
// FX Version: fx_4_0
// Child effect (requires effect pool): false
//
// 5 local buffer(s)
//
cbuffer $Globals
{
uint blendop; // Offset: 0, size: 4
}
cbuffer cb0
{
float4 QuadDesc; // Offset: 0, size: 16
float4 TexCoords; // Offset: 16, size: 16
float4 MaskTexCoords; // Offset: 32, size: 16
float4 TextColor; // Offset: 48, size: 16
}
cbuffer cb1
{
float4 BlurOffsetsH[3]; // Offset: 0, size: 48
float4 BlurOffsetsV[3]; // Offset: 48, size: 48
float4 BlurWeights[3]; // Offset: 96, size: 48
float4 ShadowColor; // Offset: 144, size: 16
}
cbuffer cb2
{
float3x3 DeviceSpaceToUserSpace; // Offset: 0, size: 44
float2 dimensions; // Offset: 48, size: 8
float3 diff; // Offset: 64, size: 12
float2 center1; // Offset: 80, size: 8
float A; // Offset: 88, size: 4
float radius1; // Offset: 92, size: 4
float sq_radius1; // Offset: 96, size: 4
}
cbuffer cb3
{
float3x3 DeviceSpaceToUserSpace_cb3;// Offset: 0, size: 44
float2 dimensions_cb3; // Offset: 48, size: 8
float2 center; // Offset: 56, size: 8
float angle; // Offset: 64, size: 4
float start_offset; // Offset: 68, size: 4
float end_offset; // Offset: 72, size: 4
}
//
// 13 local object(s)
//
Texture2D tex;
Texture2D bcktex;
Texture2D mask;
SamplerState sSampler
{
Filter = uint(MIN_MAG_MIP_LINEAR /* 21 */);
Texture = tex;
AddressU = uint(CLAMP /* 3 */);
AddressV = uint(CLAMP /* 3 */);
};
SamplerState sBckSampler
{
Filter = uint(MIN_MAG_MIP_LINEAR /* 21 */);
Texture = bcktex;
AddressU = uint(CLAMP /* 3 */);
AddressV = uint(CLAMP /* 3 */);
};
SamplerState sWrapSampler
{
Filter = uint(MIN_MAG_MIP_LINEAR /* 21 */);
Texture = tex;
AddressU = uint(WRAP /* 1 */);
AddressV = uint(WRAP /* 1 */);
};
SamplerState sMirrorSampler
{
Filter = uint(MIN_MAG_MIP_LINEAR /* 21 */);
Texture = tex;
AddressU = uint(MIRROR /* 2 */);
AddressV = uint(MIRROR /* 2 */);
};
SamplerState sMaskSampler
{
Filter = uint(MIN_MAG_MIP_LINEAR /* 21 */);
Texture = mask;
AddressU = uint(CLAMP /* 3 */);
AddressV = uint(CLAMP /* 3 */);
};
SamplerState sShadowSampler
{
Filter = uint(MIN_MAG_MIP_LINEAR /* 21 */);
Texture = tex;
AddressU = uint(BORDER /* 4 */);
AddressV = uint(BORDER /* 4 */);
BorderColor = float4(0, 0, 0, 0);
};
RasterizerState TextureRast
{
ScissorEnable = bool(TRUE /* 1 */);
CullMode = uint(NONE /* 1 */);
};
BlendState ShadowBlendH
{
BlendEnable[0] = bool(FALSE /* 0 */);
RenderTargetWriteMask[0] = byte(0x0f);
};
BlendState ShadowBlendV
{
BlendEnable[0] = bool(TRUE /* 1 */);
SrcBlend[0] = uint(ONE /* 2 */);
DestBlend[0] = uint(INV_SRC_ALPHA /* 6 */);
BlendOp[0] = uint(ADD /* 1 */);
SrcBlendAlpha[0] = uint(ONE /* 2 */);
DestBlendAlpha[0] = uint(INV_SRC_ALPHA /* 6 */);
BlendOpAlpha[0] = uint(ADD /* 1 */);
RenderTargetWriteMask[0] = byte(0x0f);
};
BlendState bTextBlend
{
AlphaToCoverageEnable = bool(FALSE /* 0 */);
BlendEnable[0] = bool(TRUE /* 1 */);
SrcBlend[0] = uint(SRC1_COLOR /* 16 */);
DestBlend[0] = uint(INV_SRC1_COLOR /* 17 */);
BlendOp[0] = uint(ADD /* 1 */);
SrcBlendAlpha[0] = uint(SRC1_ALPHA /* 18 */);
DestBlendAlpha[0] = uint(INV_SRC1_ALPHA /* 19 */);
BlendOpAlpha[0] = uint(ADD /* 1 */);
RenderTargetWriteMask[0] = byte(0x0f);
};
//
// 9 technique(s)
//
technique10 SampleTexture
{
pass P0
{
RasterizerState = TextureRast;
VertexShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Buffer Definitions:
//
// cbuffer cb0
// {
//
// float4 QuadDesc; // Offset: 0 Size: 16
// float4 TexCoords; // Offset: 16 Size: 16
// float4 MaskTexCoords; // Offset: 32 Size: 16
// float4 TextColor; // Offset: 48 Size: 16 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// cb0 cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION 0 xyz 0 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float xyzw
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c1 cb0 0 3 ( FLT, FLT, FLT, FLT)
//
//
// Runtime generated constant mappings:
//
// Target Reg Constant Description
// ---------- --------------------------------------------------
// c0 Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
vs_2_x
def c4, 0, 1, 0, 0
dcl_texcoord v0
mad oT0.xy, v0, c2.zwzw, c2
mad oT0.zw, v0.xyyx, c3.xywz, c3.xyyx
mad r0.xy, v0, c1.zwzw, c1
add oPos.xy, r0, c0
mov oPos.zw, c4.xyxy
// approximately 5 instruction slots used
vs_4_0
dcl_constantbuffer cb0[3], immediateIndexed
dcl_input v0.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xy
dcl_output o1.zw
mad o0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx
mov o0.zw, l(0,0,0,1.000000)
mad o1.xy, v0.xyxx, cb0[1].zwzz, cb0[1].xyxx
mad o1.zw, v0.xxxy, cb0[2].zzzw, cb0[2].xxxy
ret
// Approximately 5 instruction slots used
};
GeometryShader = NULL;
PixelShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// sSampler sampler NA NA 0 1
// tex texture float4 2d 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Target 0 xyzw 0 TARGET float xyzw
//
//
// Sampler/Resource to DX9 shader sampler mappings:
//
// Target Sampler Source Sampler Source Resource
// -------------- --------------- ----------------
// s0 s0 t0
//
//
// Level9 shader bytecode:
//
ps_2_x
dcl t0
dcl_2d s0
texld r0, t0, s0
mov oC0, r0
// approximately 2 instruction slots used (1 texture, 1 arithmetic)
ps_4_0
dcl_sampler s0, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_input_ps linear v1.xy
dcl_output o0.xyzw
sample o0.xyzw, v1.xyxx, t0.xyzw, s0
ret
// Approximately 2 instruction slots used
};
}
}
technique10 SampleTextureForSeparableBlending_1
{
pass P0
{
RasterizerState = TextureRast;
VertexShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Buffer Definitions:
//
// cbuffer cb0
// {
//
// float4 QuadDesc; // Offset: 0 Size: 16
// float4 TexCoords; // Offset: 16 Size: 16
// float4 MaskTexCoords; // Offset: 32 Size: 16
// float4 TextColor; // Offset: 48 Size: 16 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// cb0 cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION 0 xyz 0 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float xyzw
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c1 cb0 0 3 ( FLT, FLT, FLT, FLT)
//
//
// Runtime generated constant mappings:
//
// Target Reg Constant Description
// ---------- --------------------------------------------------
// c0 Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
vs_2_x
def c4, 0, 1, 0, 0
dcl_texcoord v0
mad oT0.xy, v0, c2.zwzw, c2
mad oT0.zw, v0.xyyx, c3.xywz, c3.xyyx
mad r0.xy, v0, c1.zwzw, c1
add oPos.xy, r0, c0
mov oPos.zw, c4.xyxy
// approximately 5 instruction slots used
vs_4_0
dcl_constantbuffer cb0[3], immediateIndexed
dcl_input v0.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xy
dcl_output o1.zw
mad o0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx
mov o0.zw, l(0,0,0,1.000000)
mad o1.xy, v0.xyxx, cb0[1].zwzz, cb0[1].xyxx
mad o1.zw, v0.xxxy, cb0[2].zzzw, cb0[2].xxxy
ret
// Approximately 5 instruction slots used
};
GeometryShader = NULL;
PixelShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Buffer Definitions:
//
// cbuffer $Globals
// {
//
// uint blendop; // Offset: 0 Size: 4
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// sSampler sampler NA NA 0 1
// sBckSampler sampler NA NA 1 1
// tex texture float4 2d 0 1
// bcktex texture float4 2d 1 1
// $Globals cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Target 0 xyzw 0 TARGET float xyzw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c0 cb0 0 1 (UINT, FLT, FLT, FLT)
//
//
// Sampler/Resource to DX9 shader sampler mappings:
//
// Target Sampler Source Sampler Source Resource
// -------------- --------------- ----------------
// s0 s0 t0
// s1 s1 t1
//
//
// Level9 shader bytecode:
//
ps_2_x
def c1, -1, -2, -3, -4
def c2, 1, 0, 0.5, -2
def c3, -5, 0, 0, 0
dcl t0
dcl_2d s0
dcl_2d s1
mov r0.w, c0.x
add r0.x, r0.w, c3.x
mul r0.x, r0.x, r0.x
texld r1, t0, s1
texld r2, t0, s0
rcp r0.y, r2.w
mad r3.xyz, r2, r0.y, -c2.x
mul r3.xyz, r3, r3
mad r4.xyz, r2, -r0.y, c2.x
rcp r3.w, r4.x
rcp r4.w, r1.w
mul r5.xyz, r1, r4.w
mad r1.xyz, r1, -r4.w, c2.z
mul r3.w, r3.w, r5.x
min r4.w, r3.w, c2.x
cmp r4.w, -r3.x, c2.x, r4.w
mul r6.xyz, r5, r5
cmp r7.x, -r6.x, c2.y, r4.w
rcp r4.w, r4.y
mul r4.w, r4.w, r5.y
min r5.w, r4.w, c2.x
cmp r4.w, -r3.y, c2.x, r5.w
cmp r7.y, -r6.y, c2.y, r4.w
rcp r4.w, r4.z
mul r4.w, r4.w, r5.z
min r5.w, r4.w, c2.x
cmp r4.w, -r3.z, c2.x, r5.w
cmp r7.z, -r6.z, c2.y, r4.w
mul r3.xyz, r0.y, r2
mad r6.xyz, r2, r0.y, r5
mad r6.xyz, r3, -r5, r6
max r8.xyz, r3, r5
cmp r0.xyz, -r0.x, r8, r7
add r7, r0.w, c1
mul r7, r7, r7
min r8.xyz, r5, r3
cmp r0.xyz, -r7.w, r8, r0
mad r8.xyz, r5, -c2.w, -c2.x
add r8.xyz, -r8, c2.x
mad r4.xyz, r4, -r8, c2.x
add r8.xyz, r5, r5
mul r5.xyz, r5, r3
mul r8.xyz, r3, r8
cmp r1.xyz, r1, r8, r4
cmp r0.xyz, -r7.z, r1, r0
cmp r0.xyz, -r7.y, r6, r0
cmp r0.xyz, -r7.x, r5, r0
lrp r4.xyz, r1.w, r0, r3
mul r4.w, r1.w, r1.w
cmp r4.w, -r4.w, c2.x, c2.y
mul r0.xyz, r2.w, r4
mul r0.w, r2.w, r2.w
cmp r0.w, -r0.w, c2.x, c2.y
add r0.w, r4.w, r0.w
cmp r2.xyz, -r0.w, r0, r2
mov oC0, r2
// approximately 56 instruction slots used (2 texture, 54 arithmetic)
ps_4_0
dcl_constantbuffer cb0[1], immediateIndexed
dcl_sampler s0, mode_default
dcl_sampler s1, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_resource_texture2d (float,float,float,float) t1
dcl_input_ps linear v1.xy
dcl_output o0.xyzw
dcl_temps 7
sample r0.xyzw, v1.xyxx, t0.xyzw, s0
sample r1.xyzw, v1.xyxx, t1.xyzw, s1
eq r2.x, r0.w, l(0.000000)
eq r2.y, r1.w, l(0.000000)
or r2.x, r2.y, r2.x
if_nz r2.x
mov o0.xyzw, r0.xyzw
ret
endif
div r0.xyz, r0.xyzx, r0.wwww
div r1.xyz, r1.xyzx, r1.wwww
ieq r2.x, cb0[0].x, l(1)
if_nz r2.x
mul r2.xyz, r0.xyzx, r1.xyzx
else
ieq r2.w, cb0[0].x, l(2)
if_nz r2.w
add r3.xyz, r0.xyzx, r1.xyzx
mad r2.xyz, -r0.xyzx, r1.xyzx, r3.xyzx
else
ieq r2.w, cb0[0].x, l(3)
if_nz r2.w
ge r3.xyz, l(0.500000, 0.500000, 0.500000, 0.000000), r1.xyzx
add r4.xyz, r1.xyzx, r1.xyzx
mul r4.xyz, r0.xyzx, r4.xyzx
mad r5.xyz, r1.xyzx, l(2.000000, 2.000000, 2.000000, 0.000000), l(-1.000000, -1.000000, -1.000000, 0.000000)
add r6.xyz, -r0.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
add r5.xyz, -r5.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
mad r5.xyz, -r6.xyzx, r5.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
movc r2.xyz, r3.xyzx, r4.xyzx, r5.xyzx
else
ieq r2.w, cb0[0].x, l(4)
if_nz r2.w
min r2.xyz, r0.xyzx, r1.xyzx
else
ieq r2.w, cb0[0].x, l(5)
if_nz r2.w
max r2.xyz, r0.xyzx, r1.xyzx
else
eq r3.xyz, r1.xyzx, l(0.000000, 0.000000, 0.000000, 0.000000)
eq r4.xyz, r0.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
add r5.xyz, -r0.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
div r1.xyz, r1.xyzx, r5.xyzx
min r1.xyz, r1.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
movc r1.xyz, r4.xyzx, l(1.000000,1.000000,1.000000,0), r1.xyzx
movc r2.xyz, r3.xyzx, l(0,0,0,0), r1.xyzx
endif
endif
endif
endif
endif
add r1.x, -r1.w, l(1.000000)
mul r1.yzw, r1.wwww, r2.xxyz
mad r0.xyz, r1.xxxx, r0.xyzx, r1.yzwy
mul o0.xyz, r0.wwww, r0.xyzx
mov o0.w, r0.w
ret
// Approximately 57 instruction slots used
};
}
}
technique10 SampleTextureForSeparableBlending_2
{
pass P0
{
RasterizerState = TextureRast;
VertexShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Buffer Definitions:
//
// cbuffer cb0
// {
//
// float4 QuadDesc; // Offset: 0 Size: 16
// float4 TexCoords; // Offset: 16 Size: 16
// float4 MaskTexCoords; // Offset: 32 Size: 16
// float4 TextColor; // Offset: 48 Size: 16 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// cb0 cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION 0 xyz 0 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float xyzw
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c1 cb0 0 3 ( FLT, FLT, FLT, FLT)
//
//
// Runtime generated constant mappings:
//
// Target Reg Constant Description
// ---------- --------------------------------------------------
// c0 Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
vs_2_x
def c4, 0, 1, 0, 0
dcl_texcoord v0
mad oT0.xy, v0, c2.zwzw, c2
mad oT0.zw, v0.xyyx, c3.xywz, c3.xyyx
mad r0.xy, v0, c1.zwzw, c1
add oPos.xy, r0, c0
mov oPos.zw, c4.xyxy
// approximately 5 instruction slots used
vs_4_0
dcl_constantbuffer cb0[3], immediateIndexed
dcl_input v0.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xy
dcl_output o1.zw
mad o0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx
mov o0.zw, l(0,0,0,1.000000)
mad o1.xy, v0.xyxx, cb0[1].zwzz, cb0[1].xyxx
mad o1.zw, v0.xxxy, cb0[2].zzzw, cb0[2].xxxy
ret
// Approximately 5 instruction slots used
};
GeometryShader = NULL;
PixelShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Buffer Definitions:
//
// cbuffer $Globals
// {
//
// uint blendop; // Offset: 0 Size: 4
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// sSampler sampler NA NA 0 1
// sBckSampler sampler NA NA 1 1
// tex texture float4 2d 0 1
// bcktex texture float4 2d 1 1
// $Globals cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Target 0 xyzw 0 TARGET float xyzw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c0 cb0 0 1 (UINT, FLT, FLT, FLT)
//
//
// Sampler/Resource to DX9 shader sampler mappings:
//
// Target Sampler Source Sampler Source Resource
// -------------- --------------- ----------------
// s0 s0 t0
// s1 s1 t1
//
//
// Level9 shader bytecode:
//
ps_2_x
def c1, -7, -8, -9, -10
def c2, 1, 0, -1, 0.25
def c3, 0.5, 2, -1, 4
def c4, 16, -12, 2, 1
dcl t0
dcl_2d s0
dcl_2d s1
mov r0.w, c0.x
add r0, r0.w, c1
mul r0, r0, r0
texld r1, t0, s0
texld r2, t0, s1
rcp r3.w, r2.w
mad r3.xy, r2.yzzw, -r3.w, c2.w
mul r4.xyz, r2, r3.w
mad r5.xyz, r4, c4.x, c4.y
mad r5.xyz, r5, r4, c3.w
mul r5.xyz, r4, r5
rsq r4.w, r4.y
rcp r4.w, r4.w
cmp r4.w, r3.x, r5.y, r4.w
mad r4.w, r2.y, -r3.w, r4.w
rcp r3.x, r1.w
mul r6.xyz, r1, r3.x
mad r7.xyz, r6, c3.y, c3.z
mad r4.w, r7.y, r4.w, r4.y
mad r8.xyz, r1, -r3.x, c3.x
mad r9, r2.xyzx, -r3.w, c2.xxxw
mad r10.xyz, r6, -c4.z, c4.w
mul r10.xyz, r4, r10
mad r10.xyz, r10, -r9, r4
cmp r11.y, r8.y, r10.y, r4.w
rsq r4.w, r4.z
rcp r4.w, r4.w
cmp r4.w, r3.y, r5.z, r4.w
mad r4.w, r2.z, -r3.w, r4.w
mad r4.w, r7.z, r4.w, r4.z
cmp r11.z, r8.z, r10.z, r4.w
rsq r4.w, r4.x
rcp r4.w, r4.w
cmp r4.w, r9.w, r5.x, r4.w
mad r4.w, r2.x, -r3.w, r4.w
mad r2.xyz, r2, r3.w, c2.z
mul r2.xyz, r2, r2
mad r4.w, r7.x, r4.w, r4.x
add r3.yzw, -r7.xxyz, c2.x
mad r3.yzw, r9.xxyz, -r3, c2.x
cmp r11.x, r8.x, r10.x, r4.w
mad r5.xyz, r1, r3.x, -r4
mad r7.xyz, r1, r3.x, r4
abs r5.xyz, r5
mul r10.xyz, r4, r6
mad r7.xyz, r10, -c3.y, r7
cmp r5.xyz, -r0.w, r5, r7
cmp r5.xyz, -r0.z, r11, r5
add r7.xyz, r6, r6
mul r4.xyz, r4, r7
cmp r3.xyz, r8, r4, r3.yzww
cmp r0.yzw, -r0.y, r3.xxyz, r5.xxyz
rcp r6.w, r6.x
mad r6.w, r9.x, -r6.w, c2.x
max r3.x, r6.w, c2.y
mul r3.yzw, r6.xxyz, r6.xxyz
cmp r6.w, -r3.y, c2.y, r3.x
cmp r4.x, -r2.x, c2.x, r6.w
rcp r4.w, r6.y
mad r4.w, r9.y, -r4.w, c2.x
max r6.w, r4.w, c2.y
cmp r4.w, -r3.z, c2.y, r6.w
cmp r4.y, -r2.y, c2.x, r4.w
rcp r4.w, r6.z
mad r4.w, r9.z, -r4.w, c2.x
max r6.w, r4.w, c2.y
cmp r4.w, -r3.w, c2.y, r6.w
cmp r4.z, -r2.z, c2.x, r4.w
cmp r0.xyz, -r0.x, r4, r0.yzww
lrp r3.xyz, r2.w, r0, r6
mul r3.w, r2.w, r2.w
cmp r3.w, -r3.w, c2.x, c2.y
mul r0.xyz, r1.w, r3
mul r0.w, r1.w, r1.w
cmp r0.w, -r0.w, c2.x, c2.y
add r0.w, r3.w, r0.w
cmp r1.xyz, -r0.w, r0, r1
mov oC0, r1
// approximately 78 instruction slots used (2 texture, 76 arithmetic)
ps_4_0
dcl_constantbuffer cb0[1], immediateIndexed
dcl_sampler s0, mode_default
dcl_sampler s1, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_resource_texture2d (float,float,float,float) t1
dcl_input_ps linear v1.xy
dcl_output o0.xyzw
dcl_temps 7
sample r0.xyzw, v1.xyxx, t0.xyzw, s0
sample r1.xyzw, v1.xyxx, t1.xyzw, s1
eq r2.x, r0.w, l(0.000000)
eq r2.y, r1.w, l(0.000000)
or r2.x, r2.y, r2.x
if_nz r2.x
mov o0.xyzw, r0.xyzw
ret
endif
div r0.xyz, r0.xyzx, r0.wwww
div r1.xyz, r1.xyzx, r1.wwww
ieq r2.x, cb0[0].x, l(7)
if_nz r2.x
eq r2.xyz, r1.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
eq r3.xyz, r0.xyzx, l(0.000000, 0.000000, 0.000000, 0.000000)
add r4.xyz, -r1.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
div r4.xyz, r4.xyzx, r0.xyzx
min r4.xyz, r4.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
add r4.xyz, -r4.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
movc r3.xyz, r3.xyzx, l(0,0,0,0), r4.xyzx
movc r2.xyz, r2.xyzx, l(1.000000,1.000000,1.000000,0), r3.xyzx
else
ieq r2.w, cb0[0].x, l(8)
if_nz r2.w
ge r3.xyz, l(0.500000, 0.500000, 0.500000, 0.000000), r0.xyzx
add r4.xyz, r0.xyzx, r0.xyzx
mul r4.xyz, r1.xyzx, r4.xyzx
mad r5.xyz, r0.xyzx, l(2.000000, 2.000000, 2.000000, 0.000000), l(-1.000000, -1.000000, -1.000000, 0.000000)
add r6.xyz, -r1.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
add r5.xyz, -r5.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
mad r5.xyz, -r6.xyzx, r5.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
movc r2.xyz, r3.xyzx, r4.xyzx, r5.xyzx
else
ieq r2.w, cb0[0].x, l(9)
if_nz r2.w
ge r3.xyz, l(0.250000, 0.250000, 0.250000, 0.000000), r1.xyzx
mad r4.xyz, r1.xyzx, l(16.000000, 16.000000, 16.000000, 0.000000), l(-12.000000, -12.000000, -12.000000, 0.000000)
mad r4.xyz, r4.xyzx, r1.xyzx, l(4.000000, 4.000000, 4.000000, 0.000000)
mul r4.xyz, r1.xyzx, r4.xyzx
sqrt r5.xyz, r1.xyzx
movc r3.xyz, r3.xyzx, r4.xyzx, r5.xyzx
ge r4.xyz, l(0.500000, 0.500000, 0.500000, 0.000000), r0.xyzx
mad r5.xyz, -r0.xyzx, l(2.000000, 2.000000, 2.000000, 0.000000), l(1.000000, 1.000000, 1.000000, 0.000000)
mul r5.xyz, r1.xyzx, r5.xyzx
add r6.xyz, -r1.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
mad r5.xyz, -r5.xyzx, r6.xyzx, r1.xyzx
mad r6.xyz, r0.xyzx, l(2.000000, 2.000000, 2.000000, 0.000000), l(-1.000000, -1.000000, -1.000000, 0.000000)
add r3.xyz, -r1.xyzx, r3.xyzx
mad r3.xyz, r6.xyzx, r3.xyzx, r1.xyzx
movc r2.xyz, r4.xyzx, r5.xyzx, r3.xyzx
else
ieq r2.w, cb0[0].x, l(10)
add r3.xyz, r0.xyzx, -r1.xyzx
add r4.xyz, r0.xyzx, r1.xyzx
mul r1.xyz, r0.xyzx, r1.xyzx
mad r1.xyz, -r1.xyzx, l(2.000000, 2.000000, 2.000000, 0.000000), r4.xyzx
movc r2.xyz, r2.wwww, |r3.xyzx|, r1.xyzx
endif
endif
endif
add r1.x, -r1.w, l(1.000000)
mul r1.yzw, r1.wwww, r2.xxyz
mad r0.xyz, r1.xxxx, r0.xyzx, r1.yzwy
mul o0.xyz, r0.wwww, r0.xyzx
mov o0.w, r0.w
ret
// Approximately 66 instruction slots used
};
}
}
technique10 SampleTextureForNonSeparableBlending
{
pass P0
{
RasterizerState = TextureRast;
VertexShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Buffer Definitions:
//
// cbuffer cb0
// {
//
// float4 QuadDesc; // Offset: 0 Size: 16
// float4 TexCoords; // Offset: 16 Size: 16
// float4 MaskTexCoords; // Offset: 32 Size: 16
// float4 TextColor; // Offset: 48 Size: 16 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// cb0 cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION 0 xyz 0 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float xyzw
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c1 cb0 0 3 ( FLT, FLT, FLT, FLT)
//
//
// Runtime generated constant mappings:
//
// Target Reg Constant Description
// ---------- --------------------------------------------------
// c0 Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
vs_2_x
def c4, 0, 1, 0, 0
dcl_texcoord v0
mad oT0.xy, v0, c2.zwzw, c2
mad oT0.zw, v0.xyyx, c3.xywz, c3.xyyx
mad r0.xy, v0, c1.zwzw, c1
add oPos.xy, r0, c0
mov oPos.zw, c4.xyxy
// approximately 5 instruction slots used
vs_4_0
dcl_constantbuffer cb0[3], immediateIndexed
dcl_input v0.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xy
dcl_output o1.zw
mad o0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx
mov o0.zw, l(0,0,0,1.000000)
mad o1.xy, v0.xyxx, cb0[1].zwzz, cb0[1].xyxx
mad o1.zw, v0.xxxy, cb0[2].zzzw, cb0[2].xxxy
ret
// Approximately 5 instruction slots used
};
GeometryShader = NULL;
PixelShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Buffer Definitions:
//
// cbuffer $Globals
// {
//
// uint blendop; // Offset: 0 Size: 4
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// sSampler sampler NA NA 0 1
// sBckSampler sampler NA NA 1 1
// tex texture float4 2d 0 1
// bcktex texture float4 2d 1 1
// $Globals cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Target 0 xyzw 0 TARGET float xyzw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c0 cb0 0 1 (UINT, FLT, FLT, FLT)
//
//
// Sampler/Resource to DX9 shader sampler mappings:
//
// Target Sampler Source Sampler Source Resource
// -------------- --------------- ----------------
// s0 s0 t0
// s1 s1 t1
//
//
// Level9 shader bytecode:
//
ps_2_x
def c1, -12, -13, -14, 0
def c2, 1, 0, 0, 0
def c3, 0.300000012, 0.589999974, 0.109999999, 0
dcl t0
dcl_2d s0
dcl_2d s1
mov r0.y, c2.y
mov r1.y, c2.y
mov r2.z, c2.y
texld r3, t0, s1
texld r4, t0, s0
rcp r0.w, r4.w
mul r5.xyz, r0.w, r4
mad r6.xy, r4.yxzw, r0.w, -r5.zyzw
cmp r7.xy, r6.x, r5.yzzw, r5.zyzw
max r1.w, r5.x, r7.x
min r2.w, r7.y, r5.x
add r7.w, r1.w, -r2.w
rcp r1.w, r3.w
mul r8.xyz, r1.w, r3
mad r9.xy, r3.x, r1.w, -r8.zyzw
rcp r2.w, r9.y
mul r2.w, r2.w, r7.w
mad r10, r3.zyyz, r1.w, -r8.xxzy
mul r7.y, r2.w, r10.w
mov r9.zw, r10
cmp r1.xz, -r9.y, r9.yyww, r7.wyyw
rcp r2.w, r9.x
mul r2.w, r2.w, r7.w
mul r7.x, r2.w, r9.z
cmp r2.xy, -r9.x, r9.xzzw, r7.wxzw
cmp r1.xyz, r9.w, r1, r2
rcp r5.w, r9.w
mul r5.w, r5.w, r7.w
mul r7.z, r5.w, r9.y
cmp r0.xz, -r10.w, r9.yyww, r7.zyww
cmp r0.xyz, r10.x, r0, r1
mov r1.x, c2.y
mov r2.x, c2.y
mov r11.z, c2.y
rcp r2.w, r9.z
mul r2.w, r2.w, r7.w
mul r7.x, r2.w, r9.x
cmp r11.xy, -r10.z, r9.xzzw, r7.xwzw
rcp r2.w, r10.y
mul r2.w, r2.w, r7.w
mul r7.y, r2.w, r10.x
cmp r2.yz, -r10.y, r10.xyxw, r7.xwyw
cmp r2.xyz, r10.x, r2, r11
rcp r2.w, r10.x
mul r2.w, r2.w, r7.w
mul r7.z, r2.w, r10.y
cmp r1.yz, -r10.x, r10.xyxw, r7.xzww
cmp r1.xyz, r9.w, r1, r2
cmp r0.xyz, r10.y, r1, r0
cmp r1.xy, r9.z, r8.yzzw, r8.zyzw
dp3 r5.w, r0, c3
dp3 r1.z, r8, c3
add r5.w, -r5.w, r1.z
add r0.xyz, r0, r5.w
add r5.w, -r0.y, r0.x
cmp r2.xy, r5.w, r0.yxzw, r0
min r5.w, r0.z, r2.x
max r7.x, r2.y, r0.z
dp3 r2.x, r0, c3
add r2.y, -r5.w, r2.x
rcp r2.y, r2.y
add r7.yzw, r0.xxyz, -r2.x
mul r7.yzw, r2.x, r7
mad r2.yzw, r7, r2.y, r2.x
cmp r0.xyz, r5.w, r0, r2.yzww
add r2.yzw, -r2.x, r0.xxyz
add r5.w, -r2.x, c2.x
mul r2.yzw, r2, r5.w
add r5.w, -r2.x, r7.x
add r7.x, -r7.x, c2.x
rcp r5.w, r5.w
mad r2.xyz, r2.yzww, r5.w, r2.x
cmp r0.xyz, r7.x, r0, r2
dp3 r5.w, r5, c3
add r2.x, r1.z, -r5.w
add r5.w, -r1.z, r5.w
mad r2.yzw, r3.xxyz, r1.w, r5.w
mad r3.xyz, r4, r0.w, r2.x
mad r7, r4.zyzx, r0.w, -r5.xxyz
add r0.w, -r3.y, r3.x
cmp r8.yz, r0.w, r3.xyxw, r3.xxyw
min r0.w, r3.z, r8.y
max r1.w, r8.z, r3.z
dp3 r5.w, r3, c3
add r2.x, -r0.w, r5.w
rcp r2.x, r2.x
add r8.yzw, r3.xxyz, -r5.w
mul r8.yzw, r5.w, r8
mad r8.yzw, r8, r2.x, r5.w
cmp r3.xyz, r0.w, r3, r8.yzww
add r8.yzw, -r5.w, r3.xxyz
add r0.w, -r5.w, c2.x
mul r8.yzw, r0.w, r8
add r0.w, r1.w, -r5.w
add r1.w, -r1.w, c2.x
rcp r0.w, r0.w
mad r8.yzw, r8, r0.w, r5.w
cmp r3.xyz, r1.w, r3, r8.yzww
add r0.w, -r2.z, r2.y
cmp r8.yz, r0.w, r2.xzyw, r2
min r0.w, r2.w, r8.y
max r1.w, r8.z, r2.w
dp3 r5.w, r2.yzww, c3
add r2.x, -r0.w, r5.w
rcp r2.x, r2.x
add r8.yzw, r2, -r5.w
mul r8.yzw, r5.w, r8
mad r8.yzw, r8, r2.x, r5.w
cmp r2.xyz, r0.w, r2.yzww, r8.yzww
add r8.yzw, -r5.w, r2.xxyz
add r0.w, -r5.w, c2.x
mul r8.yzw, r0.w, r8
add r0.w, r1.w, -r5.w
add r1.w, -r1.w, c2.x
rcp r0.w, r0.w
mad r8.yzw, r8, r0.w, r5.w
cmp r2.xyz, r1.w, r2, r8.yzww
mov r0.w, c0.x
add r8.yzw, r0.w, c1.xxyz
mul r8.yzw, r8, r8
cmp r2.xyz, -r8.w, r3, r2
cmp r0.xyz, -r8.z, r0, r2
mov r2.y, c2.y
mov r3.y, c2.y
mov r9.z, c2.y
max r0.w, r8.x, r1.x
min r2.w, r1.y, r8.x
add r10.w, r0.w, -r2.w
rcp r0.w, r7.w
mul r0.w, r0.w, r10.w
mul r10.x, r0.w, r6.x
mov r6.zw, r7.xywz
cmp r9.xy, -r7.w, r6.zxzw, r10.wxzw
rcp r0.w, r6.y
mul r0.w, r0.w, r10.w
mul r10.y, r0.w, r7.z
cmp r3.xz, -r6.y, r6.yyww, r10.wyyw
cmp r1.xyw, r7.z, r3.xyzz, r9.xyzz
rcp r0.w, r7.z
mul r0.w, r0.w, r10.w
mul r10.z, r0.w, r6.y
cmp r2.xz, -r7.z, r6.yyww, r10.zyww
cmp r1.xyw, r7.x, r2.xyzz, r1
mov r2.x, c2.y
mov r3.z, c2.y
rcp r0.w, r6.x
mul r0.w, r0.w, r10.w
mul r10.x, r0.w, r7.w
cmp r3.xy, -r6.x, r6.zxzw, r10.xwzw
rcp r0.w, r7.y
mul r0.w, r0.w, r10.w
mul r10.y, r0.w, r7.x
cmp r2.yz, -r7.y, r7.xyxw, r10.xwyw
cmp r2.xyz, r7.x, r2, r3
mov r3.x, c2.y
rcp r0.w, r7.x
mul r0.w, r0.w, r10.w
mul r10.z, r0.w, r7.y
cmp r3.yz, -r7.x, r7.xyxw, r10.xzww
cmp r2.xyz, r7.z, r3, r2
cmp r1.xyw, r7.y, r2.xyzz, r1
dp3 r0.w, r1.xyww, c3
add r0.w, -r0.w, r1.z
add r1.xyz, r0.w, r1.xyww
add r0.w, -r1.y, r1.x
cmp r2.xy, r0.w, r1.yxzw, r1
min r0.w, r1.z, r2.x
max r5.w, r2.y, r1.z
dp3 r1.w, r1, c3
add r2.xyz, -r1.w, r1
mul r2.xyz, r1.w, r2
add r2.w, -r0.w, r1.w
rcp r2.w, r2.w
mad r2.xyz, r2, r2.w, r1.w
cmp r1.xyz, r0.w, r1, r2
add r2.xyz, -r1.w, r1
add r0.w, -r1.w, c2.x
mul r2.xyz, r0.w, r2
add r0.w, -r1.w, r5.w
add r2.w, -r5.w, c2.x
rcp r0.w, r0.w
mad r2.xyz, r2, r0.w, r1.w
cmp r1.xyz, r2.w, r1, r2
cmp r0.xyz, -r8.y, r1, r0
lrp r1.xyz, r3.w, r0, r5
mul r1.w, r3.w, r3.w
cmp r1.w, -r1.w, c2.x, c2.y
mul r0.xyz, r4.w, r1
mul r0.w, r4.w, r4.w
cmp r0.w, -r0.w, c2.x, c2.y
add r0.w, r1.w, r0.w
cmp r4.xyz, -r0.w, r0, r4
mov oC0, r4
// approximately 193 instruction slots used (2 texture, 191 arithmetic)
ps_4_0
dcl_constantbuffer cb0[1], immediateIndexed
dcl_sampler s0, mode_default
dcl_sampler s1, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_resource_texture2d (float,float,float,float) t1
dcl_input_ps linear v1.xy
dcl_output o0.xyzw
dcl_temps 9
sample r0.xyzw, v1.xyxx, t0.xyzw, s0
sample r1.xyzw, v1.xyxx, t1.xyzw, s1
eq r2.x, r0.w, l(0.000000)
eq r2.y, r1.w, l(0.000000)
or r2.x, r2.y, r2.x
if_nz r2.x
mov o0.xyzw, r0.xyzw
ret
endif
div r0.xyz, r0.xyzx, r0.wwww
div r1.xyz, r1.xyzx, r1.wwww
ieq r2.x, cb0[0].x, l(12)
if_nz r2.x
max r2.x, r1.z, r1.y
max r2.x, r1.x, r2.x
min r2.y, r1.z, r1.y
min r2.y, r1.x, r2.y
add r2.w, -r2.y, r2.x
ge r3.x, r0.y, r0.x
if_nz r3.x
add r3.xyzw, -r0.xxzz, r0.yzxy
lt r4.xyz, l(0.000000, 0.000000, 0.000000, 0.000000), r3.yxwy
div r5.xyz, r2.wwww, r3.yxwy
mul r2.xyz, r3.xyzx, r5.xyzx
movc r5.yz, r4.xxxx, r2.xxwx, r3.xxyx
ge r4.xw, r0.zzzz, r0.yyyx
movc r6.yz, r4.yyyy, r2.wwyw, r3.xxyx
movc r3.xy, r4.zzzz, r2.zwzz, r3.zwzz
mov r6.x, l(0)
mov r3.z, l(0)
movc r3.xyz, r4.wwww, r6.xyzx, r3.xyzx
mov r5.x, l(0)
movc r3.xyz, r4.xxxx, r5.xyzx, r3.xyzx
else
add r4.xyzw, -r0.yyzz, r0.xzyx
lt r5.xyz, l(0.000000, 0.000000, 0.000000, 0.000000), r4.yxwy
div r6.xyz, r2.wwww, r4.yxwy
mul r2.xyz, r4.xyzx, r6.xyzx
movc r6.xz, r5.xxxx, r2.xxwx, r4.xxyx
ge r5.xw, r0.zzzz, r0.xxxy
movc r7.xz, r5.yyyy, r2.wwyw, r4.xxyx
movc r2.xy, r5.zzzz, r2.wzww, r4.wzww
mov r7.y, l(0)
mov r2.z, l(0)
movc r2.xyz, r5.wwww, r7.xyzx, r2.xyzx
mov r6.y, l(0)
movc r3.xyz, r5.xxxx, r6.xyzx, r2.xyzx
endif
dp3 r2.x, r1.xyzx, l(0.300000, 0.590000, 0.110000, 0.000000)
dp3 r2.y, r3.xyzx, l(0.300000, 0.590000, 0.110000, 0.000000)
add r2.x, -r2.y, r2.x
add r2.xyz, r2.xxxx, r3.xyzx
dp3 r2.w, r2.xyzx, l(0.300000, 0.590000, 0.110000, 0.000000)
min r3.x, r2.y, r2.x
min r3.x, r2.z, r3.x
max r3.y, r2.y, r2.x
max r3.y, r2.z, r3.y
lt r3.z, r3.x, l(0.000000)
add r4.xyz, -r2.wwww, r2.xyzx
mul r4.xyz, r2.wwww, r4.xyzx
add r3.x, r2.w, -r3.x
div r4.xyz, r4.xyzx, r3.xxxx
add r4.xyz, r2.wwww, r4.xyzx
movc r2.xyz, r3.zzzz, r4.xyzx, r2.xyzx
lt r3.x, l(1.000000), r3.y
add r4.xyz, -r2.wwww, r2.xyzx
add r3.z, -r2.w, l(1.000000)
mul r4.xyz, r3.zzzz, r4.xyzx
add r3.y, -r2.w, r3.y
div r3.yzw, r4.xxyz, r3.yyyy
add r3.yzw, r2.wwww, r3.yyzw
movc r2.xyz, r3.xxxx, r3.yzwy, r2.xyzx
else
ieq r2.w, cb0[0].x, l(13)
if_nz r2.w
max r2.w, r0.z, r0.y
max r2.w, r0.x, r2.w
min r3.x, r0.z, r0.y
min r3.x, r0.x, r3.x
add r3.w, r2.w, -r3.x
ge r2.w, r1.y, r1.x
if_nz r2.w
add r4.xyzw, -r1.xxzz, r1.yzxy
lt r5.xyz, l(0.000000, 0.000000, 0.000000, 0.000000), r4.yxwy
div r6.xyz, r3.wwww, r4.yxwy
mul r3.xyz, r4.xyzx, r6.xyzx
movc r6.yz, r5.xxxx, r3.xxwx, r4.xxyx
ge r5.xw, r1.zzzz, r1.yyyx
movc r7.yz, r5.yyyy, r3.wwyw, r4.xxyx
movc r4.xy, r5.zzzz, r3.zwzz, r4.zwzz
mov r7.x, l(0)
mov r4.z, l(0)
movc r4.xyz, r5.wwww, r7.xyzx, r4.xyzx
mov r6.x, l(0)
movc r4.xyz, r5.xxxx, r6.xyzx, r4.xyzx
else
add r5.xyzw, -r1.yyzz, r1.xzyx
lt r6.xyz, l(0.000000, 0.000000, 0.000000, 0.000000), r5.yxwy
div r7.xyz, r3.wwww, r5.yxwy
mul r3.xyz, r5.xyzx, r7.xyzx
movc r7.xz, r6.xxxx, r3.xxwx, r5.xxyx
ge r6.xw, r1.zzzz, r1.xxxy
movc r8.xz, r6.yyyy, r3.wwyw, r5.xxyx
movc r3.xy, r6.zzzz, r3.wzww, r5.wzww
mov r8.y, l(0)
mov r3.z, l(0)
movc r3.xyz, r6.wwww, r8.xyzx, r3.xyzx
mov r7.y, l(0)
movc r4.xyz, r6.xxxx, r7.xyzx, r3.xyzx
endif
dp3 r2.w, r1.xyzx, l(0.300000, 0.590000, 0.110000, 0.000000)
dp3 r3.x, r4.xyzx, l(0.300000, 0.590000, 0.110000, 0.000000)
add r2.w, r2.w, -r3.x
add r3.xyz, r2.wwww, r4.xyzx
dp3 r2.w, r3.xyzx, l(0.300000, 0.590000, 0.110000, 0.000000)
min r3.w, r3.y, r3.x
min r3.w, r3.z, r3.w
max r4.x, r3.y, r3.x
max r4.x, r3.z, r4.x
lt r4.y, r3.w, l(0.000000)
add r5.xyz, -r2.wwww, r3.xyzx
mul r5.xyz, r2.wwww, r5.xyzx
add r3.w, r2.w, -r3.w
div r5.xyz, r5.xyzx, r3.wwww
add r5.xyz, r2.wwww, r5.xyzx
movc r3.xyz, r4.yyyy, r5.xyzx, r3.xyzx
lt r3.w, l(1.000000), r4.x
add r4.yzw, -r2.wwww, r3.xxyz
add r5.x, -r2.w, l(1.000000)
mul r4.yzw, r4.yyzw, r5.xxxx
add r4.x, -r2.w, r4.x
div r4.xyz, r4.yzwy, r4.xxxx
add r4.xyz, r2.wwww, r4.xyzx
movc r2.xyz, r3.wwww, r4.xyzx, r3.xyzx
else
ieq r2.w, cb0[0].x, l(14)
if_nz r2.w
dp3 r2.w, r1.xyzx, l(0.300000, 0.590000, 0.110000, 0.000000)
dp3 r3.x, r0.xyzx, l(0.300000, 0.590000, 0.110000, 0.000000)
add r2.w, r2.w, -r3.x
add r3.xyz, r0.xyzx, r2.wwww
dp3 r2.w, r3.xyzx, l(0.300000, 0.590000, 0.110000, 0.000000)
min r3.w, r3.y, r3.x
min r3.w, r3.z, r3.w
max r4.x, r3.y, r3.x
max r4.x, r3.z, r4.x
lt r4.y, r3.w, l(0.000000)
add r5.xyz, -r2.wwww, r3.xyzx
mul r5.xyz, r2.wwww, r5.xyzx
add r3.w, r2.w, -r3.w
div r5.xyz, r5.xyzx, r3.wwww
add r5.xyz, r2.wwww, r5.xyzx
movc r3.xyz, r4.yyyy, r5.xyzx, r3.xyzx
lt r3.w, l(1.000000), r4.x
add r4.yzw, -r2.wwww, r3.xxyz
add r5.x, -r2.w, l(1.000000)
mul r4.yzw, r4.yyzw, r5.xxxx
add r4.x, -r2.w, r4.x
div r4.xyz, r4.yzwy, r4.xxxx
add r4.xyz, r2.wwww, r4.xyzx
movc r2.xyz, r3.wwww, r4.xyzx, r3.xyzx
else
dp3 r2.w, r0.xyzx, l(0.300000, 0.590000, 0.110000, 0.000000)
dp3 r3.x, r1.xyzx, l(0.300000, 0.590000, 0.110000, 0.000000)
add r2.w, r2.w, -r3.x
add r1.xyz, r1.xyzx, r2.wwww
dp3 r2.w, r1.xyzx, l(0.300000, 0.590000, 0.110000, 0.000000)
min r3.x, r1.y, r1.x
min r3.x, r1.z, r3.x
max r3.y, r1.y, r1.x
max r3.y, r1.z, r3.y
lt r3.z, r3.x, l(0.000000)
add r4.xyz, r1.xyzx, -r2.wwww
mul r4.xyz, r2.wwww, r4.xyzx
add r3.x, r2.w, -r3.x
div r4.xyz, r4.xyzx, r3.xxxx
add r4.xyz, r2.wwww, r4.xyzx
movc r1.xyz, r3.zzzz, r4.xyzx, r1.xyzx
lt r3.x, l(1.000000), r3.y
add r4.xyz, -r2.wwww, r1.xyzx
add r3.z, -r2.w, l(1.000000)
mul r4.xyz, r3.zzzz, r4.xyzx
add r3.y, -r2.w, r3.y
div r3.yzw, r4.xxyz, r3.yyyy
add r3.yzw, r2.wwww, r3.yyzw
movc r2.xyz, r3.xxxx, r3.yzwy, r1.xyzx
endif
endif
endif
add r1.x, -r1.w, l(1.000000)
mul r1.yzw, r1.wwww, r2.xxyz
mad r0.xyz, r1.xxxx, r0.xyzx, r1.yzwy
mul o0.xyz, r0.wwww, r0.xyzx
mov o0.w, r0.w
ret
// Approximately 195 instruction slots used
};
}
}
technique10 SampleRadialGradient
{
pass APos
{
RasterizerState = TextureRast;
VertexShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Buffer Definitions:
//
// cbuffer cb0
// {
//
// float4 QuadDesc; // Offset: 0 Size: 16
// float4 TexCoords; // Offset: 16 Size: 16 [unused]
// float4 MaskTexCoords; // Offset: 32 Size: 16
// float4 TextColor; // Offset: 48 Size: 16 [unused]
//
// }
//
// cbuffer cb2
// {
//
// float3x3 DeviceSpaceToUserSpace; // Offset: 0 Size: 44
// float2 dimensions; // Offset: 48 Size: 8
// float3 diff; // Offset: 64 Size: 12 [unused]
// float2 center1; // Offset: 80 Size: 8 [unused]
// float A; // Offset: 88 Size: 4 [unused]
// float radius1; // Offset: 92 Size: 4 [unused]
// float sq_radius1; // Offset: 96 Size: 4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// cb0 cbuffer NA NA 0 1
// cb2 cbuffer NA NA 1 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION 0 xyz 0 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float xyzw
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c1 cb0 0 1 ( FLT, FLT, FLT, FLT)
// c2 cb0 2 1 ( FLT, FLT, FLT, FLT)
// c3 cb1 0 2 ( FLT, FLT, FLT, FLT)
// c5 cb1 3 1 ( FLT, FLT, FLT, FLT)
//
//
// Runtime generated constant mappings:
//
// Target Reg Constant Description
// ---------- --------------------------------------------------
// c0 Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
vs_2_x
def c6, 1, 0.5, 0, 0
dcl_texcoord v0
mad oT0.xy, v0, c2.zwzw, c2
mad r0.xy, v0, c1.zwzw, c1
add r0.z, r0.x, c6.x
mul r0.z, r0.z, c5.x
mul r1.x, r0.z, c6.y
add r0.z, -r0.y, c6.x
add oPos.xy, r0, c0
mul r0.x, r0.z, c5.y
mul r1.y, r0.x, c6.y
mov r1.z, c6.x
dp3 oT0.w, r1, c3
dp3 oT0.z, r1, c4
mov oPos.zw, c6.xyzx
// approximately 13 instruction slots used
vs_4_0
dcl_constantbuffer cb0[3], immediateIndexed
dcl_constantbuffer cb1[4], immediateIndexed
dcl_input v0.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xy
dcl_output o1.zw
dcl_temps 2
mov o0.zw, l(0,0,0,1.000000)
mad r0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx
mov o0.xy, r0.xyxx
add r0.x, r0.x, l(1.000000)
add r0.y, -r0.y, l(1.000000)
mul r0.xy, r0.xyxx, cb1[3].xyxx
mul r1.xy, r0.xyxx, l(0.500000, 0.500000, 0.000000, 0.000000)
mov r1.z, l(1.000000)
dp3 o1.z, r1.xyzx, cb1[0].xyzx
dp3 o1.w, r1.xyzx, cb1[1].xyzx
mad o1.xy, v0.xyxx, cb0[2].zwzz, cb0[2].xyxx
ret
// Approximately 12 instruction slots used
};
GeometryShader = NULL;
PixelShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Buffer Definitions:
//
// cbuffer cb2
// {
//
// float3x3 DeviceSpaceToUserSpace; // Offset: 0 Size: 44 [unused]
// float2 dimensions; // Offset: 48 Size: 8 [unused]
// float3 diff; // Offset: 64 Size: 12
// float2 center1; // Offset: 80 Size: 8
// float A; // Offset: 88 Size: 4
// float radius1; // Offset: 92 Size: 4
// float sq_radius1; // Offset: 96 Size: 4
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// sSampler sampler NA NA 0 1
// sMaskSampler sampler NA NA 1 1
// tex texture float4 2d 0 1
// mask texture float4 2d 1 1
// cb2 cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Target 0 xyzw 0 TARGET float xyzw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c0 cb0 4 3 ( FLT, FLT, FLT, FLT)
//
//
// Sampler/Resource to DX9 shader sampler mappings:
//
// Target Sampler Source Sampler Source Resource
// -------------- --------------- ----------------
// s0 s0 t0
// s1 s1 t1
//
//
// Level9 shader bytecode:
//
ps_2_x
def c3, 0.5, 0, 0, 0
def c4, 1, -1, 0, -0
dcl t0
dcl_2d s0
dcl_2d s1
add r0.xy, t0.wzzw, -c1
dp2add r0.w, r0, r0, -c2.x
mul r0.w, r0.w, c1.z
mov r0.z, c1.w
dp3 r0.x, r0, c0
mad r0.y, r0.x, r0.x, -r0.w
abs r0.z, r0.y
rsq r0.z, r0.z
rcp r1.x, r0.z
mov r1.yz, -r1.x
add r0.xzw, r0.x, r1.xyyz
rcp r1.x, c1.z
mul r0.xzw, r0, r1.x
mov r1.w, c1.w
mad r1.xyz, r0.xzww, c0.z, r1.w
cmp r2.x, r1.x, r0.x, r0.w
cmp r0.xzw, r1.xyyz, c4.xyxy, c4.zyzw
mov r2.y, c3.x
texld r1, t0, s1
texld r2, r2, s0
mul r2.xyz, r2.w, r2
mul r1, r1.w, r2
add r0.w, r0.w, r0.x
cmp r0.x, r0.w, r0.x, r0.z
cmp r1, -r0.x, c4.z, r1
cmp r0, r0.y, r1, c4.z
mov oC0, r0
// approximately 28 instruction slots used (2 texture, 26 arithmetic)
ps_4_0
dcl_constantbuffer cb0[7], immediateIndexed
dcl_sampler s0, mode_default
dcl_sampler s1, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_resource_texture2d (float,float,float,float) t1
dcl_input_ps linear v1.xy
dcl_input_ps linear v1.zw
dcl_output o0.xyzw
dcl_temps 3
add r0.xy, v1.zwzz, -cb0[5].xyxx
mov r0.z, cb0[5].w
dp3 r0.z, r0.xyzx, cb0[4].xyzx
dp2 r0.x, r0.xyxx, r0.xyxx
add r0.x, r0.x, -cb0[6].x
mul r0.x, r0.x, cb0[5].z
mad r0.x, r0.z, r0.z, -r0.x
lt r0.y, r0.x, l(0.000000)
sqrt r1.x, |r0.x|
mov r1.y, -r1.x
add r0.xz, r0.zzzz, r1.xxyx
div r0.xz, r0.xxzx, cb0[5].zzzz
mul r1.xy, r0.xzxx, cb0[4].zzzz
ge r1.xy, r1.xyxx, -cb0[5].wwww
and r1.xy, r1.xyxx, l(0x3f800000, 0x3f800000, 0, 0)
add r0.x, -r0.z, r0.x
mad r2.x, r1.x, r0.x, r0.z
mov r2.y, l(0.500000)
sample r2.xyzw, r2.xyxx, t0.xyzw, s0
if_nz r0.y
mov o0.xyzw, l(0,0,0,0)
ret
endif
max r0.x, r1.y, r1.x
ge r0.x, l(0.000000), r0.x
if_nz r0.x
mov o0.xyzw, l(0,0,0,0)
ret
endif
mul r2.xyz, r2.wwww, r2.xyzx
sample r0.xyzw, v1.xyxx, t1.xyzw, s1
mul o0.xyzw, r0.wwww, r2.xyzw
ret
// Approximately 33 instruction slots used
};
}
pass A0
{
RasterizerState = TextureRast;
VertexShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Buffer Definitions:
//
// cbuffer cb0
// {
//
// float4 QuadDesc; // Offset: 0 Size: 16
// float4 TexCoords; // Offset: 16 Size: 16 [unused]
// float4 MaskTexCoords; // Offset: 32 Size: 16
// float4 TextColor; // Offset: 48 Size: 16 [unused]
//
// }
//
// cbuffer cb2
// {
//
// float3x3 DeviceSpaceToUserSpace; // Offset: 0 Size: 44
// float2 dimensions; // Offset: 48 Size: 8
// float3 diff; // Offset: 64 Size: 12 [unused]
// float2 center1; // Offset: 80 Size: 8 [unused]
// float A; // Offset: 88 Size: 4 [unused]
// float radius1; // Offset: 92 Size: 4 [unused]
// float sq_radius1; // Offset: 96 Size: 4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// cb0 cbuffer NA NA 0 1
// cb2 cbuffer NA NA 1 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION 0 xyz 0 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float xyzw
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c1 cb0 0 1 ( FLT, FLT, FLT, FLT)
// c2 cb0 2 1 ( FLT, FLT, FLT, FLT)
// c3 cb1 0 2 ( FLT, FLT, FLT, FLT)
// c5 cb1 3 1 ( FLT, FLT, FLT, FLT)
//
//
// Runtime generated constant mappings:
//
// Target Reg Constant Description
// ---------- --------------------------------------------------
// c0 Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
vs_2_x
def c6, 1, 0.5, 0, 0
dcl_texcoord v0
mad oT0.xy, v0, c2.zwzw, c2
mad r0.xy, v0, c1.zwzw, c1
add r0.z, r0.x, c6.x
mul r0.z, r0.z, c5.x
mul r1.x, r0.z, c6.y
add r0.z, -r0.y, c6.x
add oPos.xy, r0, c0
mul r0.x, r0.z, c5.y
mul r1.y, r0.x, c6.y
mov r1.z, c6.x
dp3 oT0.w, r1, c3
dp3 oT0.z, r1, c4
mov oPos.zw, c6.xyzx
// approximately 13 instruction slots used
vs_4_0
dcl_constantbuffer cb0[3], immediateIndexed
dcl_constantbuffer cb1[4], immediateIndexed
dcl_input v0.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xy
dcl_output o1.zw
dcl_temps 2
mov o0.zw, l(0,0,0,1.000000)
mad r0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx
mov o0.xy, r0.xyxx
add r0.x, r0.x, l(1.000000)
add r0.y, -r0.y, l(1.000000)
mul r0.xy, r0.xyxx, cb1[3].xyxx
mul r1.xy, r0.xyxx, l(0.500000, 0.500000, 0.000000, 0.000000)
mov r1.z, l(1.000000)
dp3 o1.z, r1.xyzx, cb1[0].xyzx
dp3 o1.w, r1.xyzx, cb1[1].xyzx
mad o1.xy, v0.xyxx, cb0[2].zwzz, cb0[2].xyxx
ret
// Approximately 12 instruction slots used
};
GeometryShader = NULL;
PixelShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Buffer Definitions:
//
// cbuffer cb2
// {
//
// float3x3 DeviceSpaceToUserSpace; // Offset: 0 Size: 44 [unused]
// float2 dimensions; // Offset: 48 Size: 8 [unused]
// float3 diff; // Offset: 64 Size: 12
// float2 center1; // Offset: 80 Size: 8
// float A; // Offset: 88 Size: 4 [unused]
// float radius1; // Offset: 92 Size: 4
// float sq_radius1; // Offset: 96 Size: 4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// sSampler sampler NA NA 0 1
// sMaskSampler sampler NA NA 1 1
// tex texture float4 2d 0 1
// mask texture float4 2d 1 1
// cb2 cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Target 0 xyzw 0 TARGET float xyzw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c0 cb0 4 2 ( FLT, FLT, FLT, FLT)
//
//
// Sampler/Resource to DX9 shader sampler mappings:
//
// Target Sampler Source Sampler Source Resource
// -------------- --------------- ----------------
// s0 s0 t0
// s1 s1 t1
//
//
// Level9 shader bytecode:
//
ps_2_x
def c2, 0.5, 0, 0, 0
dcl t0
dcl_2d s0
dcl_2d s1
mul r0.w, c1.w, c1.w
add r0.xy, t0.wzzw, -c1
dp2add r0.w, r0, r0, -r0.w
mul r0.w, r0.w, c2.x
mov r0.z, c1.w
dp3 r0.x, r0, c0
rcp r0.x, r0.x
mul r0.x, r0.x, r0.w
mov r0.y, c2.x
texld r1, t0, s1
texld r2, r0, s0
mov r0.w, c1.w
mad r0.x, r0.x, -c0.z, -r0.w
mul r2.xyz, r2.w, r2
mul r1, r1.w, r2
cmp r0, r0.x, c2.y, r1
mov oC0, r0
// approximately 18 instruction slots used (2 texture, 16 arithmetic)
ps_4_0
dcl_constantbuffer cb0[6], immediateIndexed
dcl_sampler s0, mode_default
dcl_sampler s1, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_resource_texture2d (float,float,float,float) t1
dcl_input_ps linear v1.xy
dcl_input_ps linear v1.zw
dcl_output o0.xyzw
dcl_temps 2
add r0.xy, v1.zwzz, -cb0[5].xyxx
mov r0.z, cb0[5].w
dp3 r0.z, r0.xyzx, cb0[4].xyzx
dp2 r0.x, r0.xyxx, r0.xyxx
mad r0.x, -cb0[5].w, cb0[5].w, r0.x
mul r0.x, r0.x, l(0.500000)
div r0.x, r0.x, r0.z
mul r0.z, r0.x, cb0[4].z
ge r0.z, -cb0[5].w, r0.z
mov r0.y, l(0.500000)
sample r1.xyzw, r0.xyxx, t0.xyzw, s0
if_nz r0.z
mov o0.xyzw, l(0,0,0,0)
ret
endif
mul r1.xyz, r1.wwww, r1.xyzx
sample r0.xyzw, v1.xyxx, t1.xyzw, s1
mul o0.xyzw, r0.wwww, r1.xyzw
ret
// Approximately 19 instruction slots used
};
}
pass APosWrap
{
RasterizerState = TextureRast;
VertexShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Buffer Definitions:
//
// cbuffer cb0
// {
//
// float4 QuadDesc; // Offset: 0 Size: 16
// float4 TexCoords; // Offset: 16 Size: 16 [unused]
// float4 MaskTexCoords; // Offset: 32 Size: 16
// float4 TextColor; // Offset: 48 Size: 16 [unused]
//
// }
//
// cbuffer cb2
// {
//
// float3x3 DeviceSpaceToUserSpace; // Offset: 0 Size: 44
// float2 dimensions; // Offset: 48 Size: 8
// float3 diff; // Offset: 64 Size: 12 [unused]
// float2 center1; // Offset: 80 Size: 8 [unused]
// float A; // Offset: 88 Size: 4 [unused]
// float radius1; // Offset: 92 Size: 4 [unused]
// float sq_radius1; // Offset: 96 Size: 4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// cb0 cbuffer NA NA 0 1
// cb2 cbuffer NA NA 1 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION 0 xyz 0 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float xyzw
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c1 cb0 0 1 ( FLT, FLT, FLT, FLT)
// c2 cb0 2 1 ( FLT, FLT, FLT, FLT)
// c3 cb1 0 2 ( FLT, FLT, FLT, FLT)
// c5 cb1 3 1 ( FLT, FLT, FLT, FLT)
//
//
// Runtime generated constant mappings:
//
// Target Reg Constant Description
// ---------- --------------------------------------------------
// c0 Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
vs_2_x
def c6, 1, 0.5, 0, 0
dcl_texcoord v0
mad oT0.xy, v0, c2.zwzw, c2
mad r0.xy, v0, c1.zwzw, c1
add r0.z, r0.x, c6.x
mul r0.z, r0.z, c5.x
mul r1.x, r0.z, c6.y
add r0.z, -r0.y, c6.x
add oPos.xy, r0, c0
mul r0.x, r0.z, c5.y
mul r1.y, r0.x, c6.y
mov r1.z, c6.x
dp3 oT0.w, r1, c3
dp3 oT0.z, r1, c4
mov oPos.zw, c6.xyzx
// approximately 13 instruction slots used
vs_4_0
dcl_constantbuffer cb0[3], immediateIndexed
dcl_constantbuffer cb1[4], immediateIndexed
dcl_input v0.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xy
dcl_output o1.zw
dcl_temps 2
mov o0.zw, l(0,0,0,1.000000)
mad r0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx
mov o0.xy, r0.xyxx
add r0.x, r0.x, l(1.000000)
add r0.y, -r0.y, l(1.000000)
mul r0.xy, r0.xyxx, cb1[3].xyxx
mul r1.xy, r0.xyxx, l(0.500000, 0.500000, 0.000000, 0.000000)
mov r1.z, l(1.000000)
dp3 o1.z, r1.xyzx, cb1[0].xyzx
dp3 o1.w, r1.xyzx, cb1[1].xyzx
mad o1.xy, v0.xyxx, cb0[2].zwzz, cb0[2].xyxx
ret
// Approximately 12 instruction slots used
};
GeometryShader = NULL;
PixelShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 6.3.9600.16384
//
//
// Buffer Definitions:
//
// cbuffer cb2
// {
//
// float3x3 DeviceSpaceToUserSpace; // Offset: 0 Size: 44 [unused]
// float2 dimensions; // Offset: 48 Size: 8 [unused]
// float3 diff; // Offset: 64 Size: 12
// float2 center1; // Offset: 80 Size: 8
// float A; // Offset: 88 Size: 4
// float radius1; // Offset: 92 Size: 4
// float sq_radius1; // Offset: 96 Size: 4
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// sWrapSampler sampler NA NA 0 1
// sMaskSampler sampler NA NA 1 1
// tex texture float4 2d 0 1
// mask texture float4 2d 1 1
// cb2 cbuffer NA NA 0 1